Freescale Semiconductor Document Number: MPC5604P Rev. 8, 07/2012 Data Sheet: Technical Data MPC5604P 144 LQFP 100 LQFP 20 mm x 20 mm 14 mm x 14 mm Qorivva MPC5604P Microcontroller Data Sheet Up to 64 MHz, single issue, 32-bit CPU core complex 1 safety port based on FlexCAN with 32 message (e200z0h) objects and up to 7.5 Mbit/s capability usable as second CAN when not used as safety port Compliant with Power Architecture embedded category 1 FlexRay module (V2.1) with selectable dual or single channel support, 32 message objects and up to Variable Length Encoding (VLE) 10 Mbit/s Memory organization Two 10-bit analog-to-digital converters (ADC) Up to 512 KB on-chip code flash memory with ECC 2 15 input channels, 4 channels shared between the and erase/program controller two ADCs Optional 64 (4 16) KB on-chip data flash memory Conversion time < 1 s including sampling time at with ECC for EEPROM emulation full precision Up to 40 KB on-chip SRAM with ECC Programmable Cross Triggering Unit (CTU) Fail safe protection 4 analog watchdogs with interrupt capability Programmable watchdog timer On-chip CAN/UART bootstrap loader with Boot Assist Non-maskable interrupt Module (BAM) Fault collection unit 1 FlexPWM unit Nexus L2+ interface 8 complementary or independent outputs with ADC Interrupts synchronization signals 16-channel eDMA controller Polarity control, reload unit 16 priority level controller Integrated configurable dead time unit and inverter General purpose I/Os individually programmable as input, fault input pins output or special function 16-bit resolution, up to 2 f CPU 2 general purpose eTimer units Lockable configuration 6 timers each with up/down count capabilities Clock generation 16-bit resolution, cascadable counters 440 MHz main oscillator Quadrature decode with rotation direction flag 16 MHz internal RC oscillator Double buffer input capture and output compare Software controlled FMPLL capable of speeds as fast Communications interfaces as 64 MHz 2 LINFlex channels (LIN 2.1) Voltage supply 4 DSPI channels with automatic chip select 3.3 V or 5 V supply for I/Os and ADC generation On-chip single supply voltage regulator with external 1 FlexCAN interface (2.0B Active) with 32 message ballast transistor objects Operating temperature ranges: 40 to 125 C or 40 to 105 C Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale, Inc., 20082012. All rights reserved. Table of Contents 1 Introduction 3 2.2.3 Pin muxing 24 1.1 Document overview 3 3 Electrical characteristics 38 1.2 Description .3 3.1 Introduction . 38 1.3 Device comparison .3 3.2 Parameter classification . 38 1.4 Block diagram .4 3.3 Absolute maximum ratings . 39 1.5 Feature details 7 3.4 Recommended operating conditions 42 1.5.1 High performance e200z0 core processor 7 3.5 Thermal characteristics 46 1.5.2 Crossbar switch (XBAR) .8 3.5.1 Package thermal characteristics . 46 1.5.3 Enhanced direct memory access (eDMA) 8 3.5.2 General notes for specifications at maximum 1.5.4 Flash memory .8 junction temperature 47 1.5.5 Static random access memory (SRAM) 9 3.6 Electromagnetic interference (EMI) characteristics . 48 1.5.6 Interrupt controller (INTC) 9 3.7 Electrostatic discharge (ESD) characteristics . 48 1.5.7 System status and configuration module 3.8 Power management electrical characteristics . 49 (SSCM) .10 3.8.1 Voltage regulator electrical characteristics 49 1.5.8 System clocks and clock generation .10 3.8.2 Voltage monitor electrical characteristics . 52 1.5.9 Frequency-modulated phase-locked loop 3.9 Power up/down sequencing 53 (FMPLL) .10 3.10 DC electrical characteristics 55 1.5.10 Main oscillator 11 3.10.1 NVUSRO register . 55 1.5.11 Internal RC oscillator .11 3.10.2 DC electrical characteristics (5 V) 55 1.5.12 Periodic interrupt timer (PIT) .11 3.10.3 DC electrical characteristics (3.3 V) . 57 1.5.13 System timer module (STM) .11 3.10.4 Input DC electrical characteristics definition 58 1.5.14 Software watchdog timer (SWT) 11 3.10.5 I/O pad current specification . 59 1.5.15 Fault collection unit (FCU) .12 3.11 Main oscillator electrical characteristics . 64 1.5.16 System integration unit Lite (SIUL) .12 3.12 FMPLL electrical characteristics . 65 1.5.17 Boot and censorship .12 3.13 16 MHz RC oscillator electrical characteristics 67 1.5.18 Error correction status module (ECSM) .13 3.14 Analog-to-digital converter (ADC) electrical 1.5.19 Peripheral bridge (PBRIDGE) 13 characteristics . 67 1.5.20 Controller area network (FlexCAN) 13 3.14.1 Input impedance and ADC accuracy 68 1.5.21 Safety port (FlexCAN) 14 3.14.2 ADC conversion characteristics 72 1.5.22 FlexRay .14 3.15 Flash memory electrical characteristics 74 1.5.23 Serial communication interface module 3.16 AC specifications . 75 (LINFlex) 15 3.16.1 Pad AC specifications . 75 1.5.24 Deserial serial peripheral interface (DSPI) 15 3.17 AC timing characteristics . 76 1.5.25 Pulse width modulator (FlexPWM) 16 3.17.1 RESET pin characteristics 76 1.5.26 eTimer 16 3.17.2 IEEE 1149.1 interface timing 78 1.5.27 Analog-to-digital converter (ADC) module .17 3.17.3 Nexus timing 81 1.5.28 Cross triggering unit (CTU) 18 3.17.4 External interrupt timing (IRQ pin) 83 1.5.29 Nexus development interface (NDI) 18 3.17.5 DSPI timing . 84 1.5.30 Cyclic redundancy check (CRC) 19 4 Package characteristics 90 1.5.31 IEEE 1149.1 JTAG controller .19 4.1 Package mechanical data 90 1.5.32 On-chip voltage regulator (VREG) .19 4.1.1 144 LQFP mechanical outline drawing 90 2 Package pinouts and signal descriptions 20 4.1.2 100 LQFP mechanical outline drawing 92 2.1 Package pinouts 20 5 Ordering information . 96 2.2 Pin description .21 Appendix AAbbreviations . 97 2.2.1 Power supply and reference voltage pins .21 6 Document revision history . 98 2.2.2 System pins 23 MPC5604P Microcontroller Data Sheet, Rev. 8 2 Freescale