SPC5676RDK3MVU1R NXP

Freescale Semiconductor Document Number: MPC5676R Rev. 4, 16 Feb 2016 Data Sheet: Advance Information MPC5676R MPC5676R Microcontroller TEPBGA416 27 mm x 27 mm TEPBGA516 Data Sheet 27mm x 27mm On-chip modules available within the family include the Up to 96 eTPU2 channels (32 channels per eTPU2) following features: total of 36 KB code RAM total of 9 KB parameter RAM Two identical dual issue, 32-bit CPU core complexes Enhanced modular input output system supporting 32 (e200z7), each with unified channels (eMIOS) with each channel capable of Power Architecture embedded specification compliance single action, double action, pulse width modulation Instruction set enhancement allowing variable length (PWM) and modulus counter operation encoding (VLE), optional encoding of mixed 16-bit and Two enhanced queued analog-to-digital converter 32-bit instructions, for code size footprint reduction (eQADC) modules with Signal processing extension (SPE) instruction support two separate analog converters per eQADC module for digital signal processing (DSP) support for a total of 64 analog input pins, expandable to Single-precision floating point operations (FPU) 176 inputs with off-chip multiplexers 16 KB I-Cache and 16 KB D-Cache one absolute reference ADC channel Hardware cache coherency between cores interface to twelve hardware decimation filters 16 Hardware semaphores enhanced Tap command to route any conversion to two 3 channel CRC module separate decimation filters 6MB on-chip flash Temperature sensor Supports read during program and erase operations, and Five deserial serial peripheral interface (DSPI) modules multiple blocks allowing EEPROM emulation Three enhanced serial communication interface (eSCI) 384KB on-chip general-purpose SRAM including 48KB of modules standby RAM Four controller area network (FlexCAN) modules Two multi-channel direct memory access controllers Dual-channel FlexRay controller (eDMA) Nexus development interface (NDI) per IEEE-ISTO 64 channels per eDMA 5001-2003 standard, with some support for 2010 standard. Dual core Interrupt controller (INTC) Device and board test support per Joint Test Action Group Phase-locked loop with FM modulation (FMPLL) (JTAG) (IEEE 1149.1) Crossbar switch architecture for concurrent access to On-chip voltage regulator controller regulates supply peripherals, flash, or RAM from multiple bus masters voltage down to 1.2 V for core logic External Bus Interface (EBI) for calibration and Self Test capability application development System integration unit (SIU) with error correction status module (ECSM) Four protected port output pins (PPO) Boot assist module (BAM) supports serial bootload via CAN or SCI Three second-generation enhanced time processor units (eTPU2) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2016. All rights reserved.Table of Contents 1 Ordering Information .3 4.7.2 I/O Pad V Current Specifications . 24 DD33 1.1 Orderable Parts 3 4.7.3 LVDS Pad Specifications . 25 2 MPC5676R Blocks 4 4.8 Oscillator and FMPLL Electrical Characteristics . 27 2.1 Block Diagram .4 4.9 eQADC Electrical Characteristics 29 3 Pin Assignments 6 4.10 C90 Flash Memory Electrical Characteristics . 31 3.1 416-ball TEPBGA Pin Assignments 6 4.11 AC Specifications . 32 3.2 516-ball TEPBGA Pin Assignments 7 4.11.1 Clocking Modes 32 3.3 Pin Muxing and Reset States .8 4.11.2 Pad AC Specifications . 33 4 Electrical Characteristics .8 4.12 AC Timing 34 4.1 Maximum Ratings 8 4.12.1 Generic Timing Diagrams . 34 4.2 Thermal Characteristics .9 4.12.2 Reset and Configuration Pin Timing . 35 4.2.1 General Notes for Specifications at 4.12.3 IEEE 1149.1 Interface Timing 36 Maximum Junction Temperature 11 4.12.4 Nexus Timing 39 4.3 EMI (Electromagnetic Interference) Characteristics .12 4.12.5 External Bus Interface (EBI) Timing . 41 4.4 ESD Characteristics .13 4.12.6 External Interrupt Timing (IRQ Pin) . 46 4.5 PMC/POR/LVI Electrical Specifications 13 4.12.7 eTPU Timing 46 4.5.1 Regulator Example 16 4.12.8 eMIOS Timing . 47 4.6 Power Up/Down Sequencing 18 4.12.9 DSPI Timing . 48 4.6.1 Power-Up 19 5 Package Information . 54 4.6.2 Power-Down .19 5.1 416-Pin Package . 54 4.6.3 Power Sequencing and POR Dependent 5.2 516-Pin Package . 56 on V .20 6 Product Documentation . 58 DDA 4.7 DC Electrical Specifications .20 Appendix ASignal Properties and Muxing 59 4.7.1 I/O Pad Current Specifications .23 Appendix BRevision History . 109 MPC5676R Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor