Document Number VYBRIDRSERIESEC NXP Semiconductors Rev. 8, 01/2018 Data Sheet: Technical Data VYBRIDRSERIESEC VF3xxR, VF5xxR Features Debug Standard JTAG Operating characteristics 16-bit Trace port Voltage range 3 V to 3.6 V Temperature range(ambient) -40 C to 85 C Timers Motor control/general purpose timer (FTM) ARM Cortex A5 Core features Periodic Interrupt Timers (PITs) Up to 400 MHz ARM Cortex A5 core Low-power timer (LPTMR0) 32 KB/32 KB I/D L1 Cache IEEE 1588 Timer per MAC interface (part of 1.6 DMIPS/MHz based on ARMv7 architecture Ethernet Subsystem) NEON MPE (Media Processing Engine) Co- processor Communications Double Precision Floating Point Unit Six Universal asynchronous receivers/transmitters 512 KB L2 cache (on selected part numbers only) (UART)/Serial communications interface (SCI) with LIN, ISO7816, IrDA, and hardware flow control ARM Cortex M4 Core features Four Deserial Serial peripheral interface (DSPI) Up to 133 MHz ARM Cortex M4 Four Inter-Integrated Circuit (I2C) with SMBUS Integrated DSP capability support 64 KB Tightly Coupled Memory (TCM) Dual USB OTG Controller + PHY 16 KB/16 KB I/D L1 Cache Dual 4/8 bit Secure Digital Host controller 1.25 DMIPS/MHz based on ARMv7 architecture Local Media Bus (MLB50) Clocks Dual 10/100 Ethernet (IEEE 1588) 24 MHz crystal oscillator Dual FlexCAN3 32 kHz crystal oscillator Security Internal reference clocks (128 KHz and 24 MHz) ARM TrustZone including the TZ architecture Phase Locked Loops (PLLs) Secure Non-Volatile Storage (SNVS) Low Jitter Digital PLLs Real Time Clock System debug, protection, and power management Real Time Integrity Checker (RTIC) Various stop, wait, and run modes to provide low TrustZone Watchdog (TZ WDOG) power based on application needs Trust Zone Address Space Controller Peripheral clock enable register can disable clocks to Random Number Generator unused modules, thereby reducing currents Hashing Low voltage warning and detect with selectable trip Secure JTAG points Memory Interfaces Illegal opcode and illegal address detection with 8/16-bit DRAM Controller with support for programmable reset or processor exception response LPDDR2/DDR3 - Up to 400 MHz (ECC supported Hardware CRC module to support fast cyclic for 8-bit only and not 16-bit) redundancy checks (CRC) 8/16-bit NAND Flash controller with ECC (ECC 128-bit unique chip identifier supported for 8-bit only and not 16-bit) Hardware watchdog Dual Quad SPI with XIP (Execute-In-Place) External Watchdog Monitor (EWM) 8/16/32-bit External bus (Flexbus) Dual DMA controller with 32 channels (with DMAMUX) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Display and Video Dual Display Control Unit (DCU) with support for color TFT display up to WVGA Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6 Video Interface Unit (VIU) for camera Open VG Graphics Processing Unit (GPU) VideoADC Analog Dual 12-bit SAR ADC with 1MS/s Dual 12-bit DAC Audio Four Synchronous Audio Interface (SAI) Enhanced Serial Audio Interface (ESAI) Sony Philips Digital Interface (SPDIF), Rx and Tx Asynchronous Sample Rate Converter (ASRC) Human-Machine Interface (HMI) GPIO pins with interrupt support, DMA request capability, digital glitch filter. Hysteresis and configurable pull up/down device on all input pins Configurable slew rate and drive strength on all output pins On-Chip Memory 512 KB On-chip SRAM with ECC 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB graphics and 512 KB L2 cache. 96 KB Boot ROM VF3xxR, VF5xxR, Rev. 8, 01/2018 2 NXP Semiconductors