Document Number T1042 Freescale Semiconductor Rev. 2, 06/2015 Data Sheet: Technical Data T1042 QorIQ T1042, T1022 Data Sheet Features Additional peripheral interfaces Two high-speed USB 2.0 controllers with integrated e5500 cores built on Power Architecture technology, PHY T1042 has four cores and T1022 has two cores Enhanced secure digital host controller with support Each core with a private 256KB L2 cache for high capacity memory card(SD/eSDHC/eMMC) 256 KB shared L3 CoreNet platform cache (CPC) Enhanced Serial peripheral interface (eSPI) Four I2C controllers Hierarchical interconnect fabric Two DUARTs CoreNet Coherency manager supporting coherent Integrated flash controller supporting NAND and and non-coherent transactions with prioritization and NOR flash bandwidth allocation amongst CoreNet end-points Display interface unit (DIU) with 12-bit dual data 150Gbps coherent read bandwidth rate One 32-/64-bit DDR3L/DDR4 SDRAM memory TDM Interface controllers Four GPIO controllers supporting up to 109 general ECC and interleaving support purpose I/O signals Two 8-channel DMA engines Data Path Acceleration Architecture (DPAA) Multicore programmable interrupt controller (MPIC) incorporating acceleration for the following functions: Packet parsing, classification, and distribution QUICC Engine block Queue management for scheduling, packet 32-bit RISC controller for flexible support of the sequencing, and congestion management communications peripherals Hardware buffer management for buffer allocation Serial DMA channel for receive and transmit on all and de-allocation serial channels Cryptography Acceleration Two universal communication controllers, RegEx Pattern Matching Acceleration supporting TDM, HDLC and UART IEEE Std 1588 support 780 FC-PBGA package, 23 mm x 23 mm Parallel Ethernet interfaces Up to two RGMII interface One MII interface Eight SerDes lanes for high-speed peripheral interfaces Four PCI Express 2.0 controllers Two Serial ATA (SATA 3Gb/s) controllers Up to five SGMII interface supporting 1000 Mbps Up to two SGMII interface with maximum speed of 2500 Mbps Supports 1000Base-KX 2015 Freescale Semiconductor, Inc.Table of Contents 1 Overview.............................................................................................. 3 3.18 I2C interface.............................................................................. 127 2 Pin assignments.................................................................................... 4 3.19 GPIO interface...........................................................................131 2.1 780 ball layout diagrams........................................................... 4 3.20 Display interface unit................................................................ 133 2.2 Pinout list...................................................................................10 3.21 TDM interface........................................................................... 135 3 Electrical characteristics.......................................................................46 3.22 High-speed serial interfaces (HSSI).......................................... 137 3.1 Overall DC electrical characteristics.........................................46 4 Hardware design considerations...........................................................160 3.2 Power sequencing......................................................................53 4.1 System clocking........................................................................ 160 3.3 Power-down requirements.........................................................56 4.2 Power supply design..................................................................170 3.4 Power-on ramp rate................................................................... 57 4.3 Decoupling recommendations...................................................175 3.5 Power characteristics.................................................................57 4.4 SerDes block power supply decoupling recommendations.......175 3.6 Input clocks............................................................................... 61 4.5 Connection recommendations................................................... 176 3.7 RESET initialization..................................................................67 4.6 Thermal......................................................................................187 3.8 DDR4 and DDR3L SDRAM controller.................................... 68 4.7 Recommended thermal model...................................................188 3.9 eSPI interface.............................................................................75 4.8 Temperature diode.....................................................................188 3.10 DUART interface...................................................................... 78 4.9 Thermal management information............................................ 189 3.11 Ethernet interface, Ethernet management interface, IEEE Std 5 Package information.............................................................................192 1588........................................................................................... 80 5.1 Package parameters for the FC-PBGA......................................192 3.12 QUICC Engine Specifications...................................................99 5.2 Mechanical dimensions of the FC-PBGA................................. 192 3.13 USB interface............................................................................ 104 6 Security fuse processor.........................................................................194 3.14 Integrated flash controller..........................................................105 7 Ordering information............................................................................194 3.15 Enhanced secure digital host controller (eSDHC).....................113 7.1 Part numbering nomenclature....................................................194 3.16 Multicore programmable interrupt controller (MPIC).............. 122 7.2 Part marking.............................................................................. 195 3.17 JTAG controller.........................................................................124 8 Revision history....................................................................................196 QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015 2 Freescale Semiconductor, Inc.