QorIQ Communications Platforms T Series QorIQ T2080 and T2081 communication processors safe partitioning of control and data plane The four e6500 dual-threaded cores share a Overview applications within the device. low-latency backside 2 MB L2 cache, allowing The 28 nm QorIQ T2080 and T2081 efficient sharing of code and data. Each communications processors bring the Enterprise equipment: Modular Ethernet e6500 core implements the Freescale AltiVec architectural innovations of the T series switches, services cards, UTM equipment, technology-based SIMD engine, dramatically flagship T4240, such as the 1.8 GHz enterprise storage, data center boosting the performance of media and dual-threaded e6500 core, into an eight Service provider: Core and edge routers, networking algorithms, offering native inline virtual core mid-range platform at reduced broadband access, metro Ethernet, optical programming and using less power than a power and price points. networking separate DSP. The T2080 processor is primarily intended to Wireless infrastructure: Mobile backhaul, succeed our successful P3041 and P2041 Virtualization NICs, channel cards, control cards in LTE, mid-range series of quad-core devices as a The T2080 and T2081 processors include WCDMA, GSM, WiMAX control plane or integrated control and data support for hardware-assisted virtualization. Aerospace and defense: ruggedized or plane processor. It provides an excellent The e6500 core offers an extra core privilege highly secure routers, avionics networking, migration path, as it offers 2x or better in core level (hypervisor) and hardware offload of instrumentation panels, military SBCs capability, cache size, SerDes bandwidth and logical to real address translation. In addition, Ethernet connectivity within a similar power Industrial computing: SBCs, factory the T2080 and T2081 include platform-level budget. It also provides a value engineering automation, test and measurement enhancements such as SR-IOV and I/O opportunity for P4080 customers, as T2080 virtualization with DMA memory protection provides equivalent performance at much e6500 Core through IOMMUs and configurable storage lower price and power. profiles, which provide isolation of I/O buffers The T2080 and T2081 processors are The T2081 is a smaller package version of between guest environments. Virtualization based on the 64-bit e6500 core, built on the T2080, which is pin compatible with software for the T2080 and T2081 processors Power Architecture technology, and run the quad-core T1042. This provides T1042 includes kernel virtualization model (KVM), up to 1.8 GHz. The e6500 core also offers customers an easy upgrade to higher Linux containers and the Freescale higher aggregate instructions per clock at performance if processing requirements hypervisor. lower power with an innovative fused core increase. It also enables customers to reuse approach to threading. The e6500s fully a single board for two different product resourced dual threads provide 1.7 times the performance levels. performance of a single thread. Target Markets and Applications QorIQ T2080 Communications Processor QorIQ T2080 Communications Processor The T2080 and T2081 processors are T1 T2 T1 T2 T1 T2 T1 T2 targeted at mid-range control plane Power Power Power Power Architecture Architecture Architecture Architecture applications or mixed control and data e6500 e6500 e6500 e6500 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32/64-bit plane applications. The highly efficient eight D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache 512 KB Pre- DDR3/3L Platform Fetch Memory Cache 2 MB Banked L2 virtual core device achieves up to 1.8 GHz Controller Security Fuse Processor CoreNet Coherency Fabric even while maintaining a short seven-stage Security Monitor Peripheral Access PAMU PAMU Management Unit pipeline for better latency response to IFC Power Management Security Real-Time Debug unpredictable control plane code branches. Parse, Classify, DCE 5.2 Queue 2x DMA SD/MMC Watchpoint Distribute 1.0 (XOR Mgr. Cross Advanced virtualization technology facilitates 2x DUART Trigger CRC) HiGig DCB 2 4x I C Perf. Pattern Trace Monitor SPI, GPIO 1GbE 1GbE Match Buffer RMan Engine 2x USB 2.0 + PHY Mgr. Aurora 1GbE 1GbE 2.1 8-Lane 10 GHz SerDes 8-Lane 8 GHz SerDes Core Complex (CPU, L2, L3 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements PAMU 1/10 GbE 1/10 GbE 1/10 GbE 1/10 GbE PCle PCle PCle PCle sRIO sRIO SATA 2.0 SATA 2.0Data Path Acceleration T2080 vs. T2081 Differences Architecture (DPAA) T2080 T2081 The T2080 and T2081 processors integrate SerDes 16 8 the QorIQ DPAA, an innovative multicore PCIe 2x Gen3 + 2x Gen2 1x Gen3 + 3x Gen2 infrastructure for scheduling work to cores SRIO 2 + RMan No (physical and virtual), hardware accelerators SATA 2 No and network interfaces. The FMAN, a primary Aurora Yes No element of the DPAA, parses headers 10 Gb/s MACs Up to four, with XFI, XAUI, HiGig Up to 2x XFI from incoming packets and classifies and 1 Gb/s MACs Up to eight Up to seven selects data buffers with optional policing Package 25 x 25mm, 896 pins, 0.8 mm pitch 23 x 23mm, 780 pins, 0.8 mm pitch, pin compatible and congestion management. The FMAN with T1042 passes its work to the QMAN, which assigns it to cores or accelerators with a multi-level T2080 and T2081 Features List scheduling hierarchy, while maintaining packet Four dual-threaded e6500 Up to 1.8 GHz, 6.0 DMIPS/MHz per core ordering. The BMAN manages allocation and cores built on Power Shares a 2 MB L2 cache Architecture technology Three levels of instructions: User, supervisor, hypervisor de-allocation of packet buffers. The T2080 Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture and T2081s implementation of DPAA offers Advanced power saving modes include state retention power gating accelerators for cryptography, deep packet CoreNet platform cache 512 KB shared platform cache with prefetch engine inspection and compression/decompression. Hierarchical interconnect CoreNet fabric supporting coherent and non-coherent transactions with prioritization fabric and bandwidth allocation amongst CoreNet endpoints Memory controller 64-bit DDR3/3L SDRAM up to 2133 MT/s Software and Tool Support 72-bit width including ECC DPAA incorporating Packet parsing, classification and distribution to 24 Gb/s (FMAN) Freescale and our partner network deliver acceleration for the Queue management for scheduling, packet sequencing and congestion a wide range of tools, run-time software, 24 following functions management of up to 2 queues (QMAN) Hardware buffer management for buffer allocation and de-allocation with reference solutions and services to accelerate 64 buffer pools (BMAN) your designs. Cryptography acceleration to 10 Gb/s (SEC) Decompression/compression acceleration at up to 17.5 Gb/s (DCE) QorIQ T2080 reference design board DPAA chip-to-chip interconnect via RapidIO message manager (RMAN) (T2080 only) (T2080RDB) Pattern matching acceleration to 10 Gb/s (PME) CodeWarrior Development Studio for SerDes 16 lanes at up to 10 GHz (8 on T2081) Power Architecture Ethernet interfaces Quality of service: Egress traffic shaping and priority flow control for data center bridging in converged data center applications 8 MACs (7 on T2081), multiplexed over the following options: Freescale Linux SDK Up to four 10 Gb/s MACs supporting XFI/KR, XAUI and HiGig (two on T2081 supporting XFI/KR only) VortiQa Application Software Up to eight 1 Gb/s MACs (5 on T2080) supporting SGMII Up to two 2.5 Gb/s SGMII VortiQa Application Identification Up to two RGMII Software (AIS) High-speed peripheral Two PCI Express 3.0 controllers (one on T2081) interfaces Two PCI Express 2.0 controllers (three on T2081) Enterprise Software for Networking Endpoint SR-IOV Two Serial RapidIO 2.1 controllers/ports running at up to 5 GHz with Type 11 VortiQa open network switch software messaging and Type 9 data streaming support (T2080 only) Additional peripheral Two serial ATA (SATA 2.0) controllers (T2080 only) VortiQa open network director interfaces Two High-Speed USB 2.0 controllers with integrated PHYs software Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface 2 Professional Services & Support Four I C controllers Four UARTS Commercial Services Integrated flash controller supporting NAND and NOR flash memory DMA Dual eight channel Linux SDK Support Package Support for hardware Extra privileged level for hypervisor support Reference Design Software (RDS) virtualization and Logical to real address translation partitioning enforcement Virtual core aware MMU/TLB Support Package vMPIC (virtualized interrupt controller)/virtual core capable PPC cores vDMA (user level DMA engine) Third Party Software and Tools PAMU v2 (I/O MMU supporting paging) DPAA (Ethernet MAC virtualization, accelerator virtualization) Enea, Green Hills, Mentor Graphics QorIQ trust architecture Secure boot, secure debug, tamper detection (T2080 only), volatile key storage, and Wind River alternate image and key revocation For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, AltiVec, CodeWarrior and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. 2014 Freescale Semiconductor, Inc. Document Number: T2080FS REV 1