T2081NSN8PTB NXP

Document Number T2081 NXP Semiconductors Rev. 3, 03/2018 Data Sheet: Technical Data T2081 QorIQ T2081 Data Sheet Features 8 SerDes lanes at up to 10 GHz 4 e6500 cores built on Power Architecture 6 Ethernet interfaces, supporting combinations of: technology sharing a 2 MB L2 cache Up to two 10 Gbps Ethernet MACs Up to six 1 Gbps Ethernet MACs 512 KB CoreNet platform cache (CPC) Up to two 2.5Gbps Ethernet MACs Hierarchical interconnect fabric IEEE Std 1588 support CoreNet fabric supporting coherent and non- High-speed peripheral interfaces coherent transactions with prioritization and Four PCI Express controllers (two support PCIe 2.0 bandwidth allocation amongst CoreNet end-points and two support PCIe 3.0) Queue Manager (QMan) fabric supporting packet- level queue management and quality of service Additional peripheral interfaces scheduling Two high-speed USB 2.0 controllers with integrated PHY One 32-/64-bit DDR3 SDRAM memory controller Enhanced secure digital host controller (SD/MMC/ DDR3 and DDR3L with ECC and interleaving eMMC) support Enhanced Serial peripheral interface (eSPI) Memory pre-fetch engine Four I2C controllers Data Path Acceleration Architecture (DPAA) Four 2-pin UARTs or two 4-pin UARTs incorporating acceleration for the following functions: Integrated flash controller supporting NAND and Packet parsing, classification, and distribution NOR flash (Frame Manager 1.1) Three 8-channel DMA engines Queue management for scheduling, packet sequencing, and congestion management (Queue 780 FC-PBGA package, 23 mm x 23 mm, 0.8mm pitch Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (Buffer Manager 1.1) Cryptography Acceleration (SEC 5.2) RegEx Pattern Matching Acceleration (PME 2.1) Decompression/Compression Acceleration (DCE 1.0) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Overview.............................................................................................. 3 3.16 JTAG controller.........................................................................86 2 Pin assignments.................................................................................... 3 3.17 I2C interface.............................................................................. 89 2.1 784 ball layout diagrams........................................................... 4 3.18 GPIO interface...........................................................................92 2.2 Pinout list...................................................................................10 3.19 High-speed serial interfaces (HSSI).......................................... 94 3 Electrical characteristics.......................................................................39 4 Hardware design considerations...........................................................128 3.1 Overall DC electrical characteristics.........................................39 4.1 System clocking........................................................................ 128 3.2 Power sequencing......................................................................45 4.2 Power supply design..................................................................133 3.3 Power-down requirements.........................................................48 4.3 Decoupling recommendations...................................................142 3.4 Power characteristics.................................................................48 4.4 SerDes block power supply decoupling recommendations.......142 3.5 Power-on ramp rate................................................................... 53 4.5 Connection recommendations................................................... 143 3.6 Input clocks............................................................................... 54 4.6 Thermal......................................................................................149 3.7 RESET initialization..................................................................58 4.7 Recommended thermal model...................................................150 3.8 DDR3 and DDR3L SDRAM controller.................................... 59 4.8 Thermal management information............................................ 150 3.9 eSPI interface.............................................................................65 5 Package information.............................................................................152 3.10 DUART interface...................................................................... 68 5.1 Package parameters for the FC-PBGA......................................152 3.11 Ethernet interface, Ethernet management interface 1 and 2, 5.2 Mechanical dimensions of the FC-PBGA................................. 152 IEEE Std 1588........................................................................... 69 6 Security fuse processor.........................................................................154 3.12 USB interface............................................................................ 77 7 Ordering information............................................................................154 3.13 Integrated flash controller..........................................................79 7.1 Part numbering nomenclature....................................................154 3.14 Enhanced secure digital host controller (eSDHC).....................82 7.2 Orderable part numbers addressed by this document................155 3.15 Multicore programmable interrupt controller (MPIC).............. 86 8 Revision history....................................................................................157 QorIQ T2081 Data Sheet, Rev. 3, 03/2018 2 NXP Semiconductors