UJA1023 LIN-I/O slave Rev. 5 17 August 2010 Product data sheet 1. General description The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces basic components commonly used in electronic control units for input and output handling. The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is LIN 2.0 / SAE J2602 compliant and LIN 1.3 compatible, a 30 k termination resistor necessary for LIN-slaves, and eight I/O ports which are configurable via the LIN bus. An automatic bit rate synchronization circuit adapts to any (master) bit rate between 1 kbit/s and 20 kbit/s. For this, an oscillator is integrated. The LIN protocol will be handled autonomously and both Node Address (NAD) and LIN frame Identifier (ID) programming will be done by a master request and an optional slave response message in combination with a daisy chain or plug coding function. The eight bidirectional I/O pins are configurable via LIN bus messages and can have the following functions: Input: Standard input pin Local wake-up Edge capturing on falling, rising or both edges Analog input pin Switch matrix (in combination with output pins) Output: Standard output pin as high-side driver, low-side driver or push-pull driver Cyclic sense mode for local wake-up Pulse Width Modulation (PWM) mode for example, for back light illumination Switch matrix (in combination with input pins) On entering a low-power mode it is possible to hold the last output state or to change over to a user programmable output state. In case of a failure (e.g. LIN bus short to ground) the output changes over to a user programmable limp home output state and the low-power Limp home mode will be entered. Due to the advanced low-power behavior the power consumption of the UJA1023 in low-power mode is minimal.UJA1023 NXP Semiconductors LIN-I/O slave 2. Features and benefits Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s and20kbit/s Integrated LIN 2.0 / SAE J2602 transceiver (including 30 k termination resistor) Eight bidirectional I/O pins 4 2, 4 3, or 4 4 switch matrix to support reading and supplying a maximum number of 16 switches Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver 8-bit ADC Advanced low-power behavior On-chip oscillator Node Address (NAD) configuration via daisy chain or plug coding Inputs supporting local wake-up and edge capturing Configurable Sleep mode Limp home configuration in case of error conditions Extremely low electromagnetic emission High immunity against electromagnetic interference Bus line protected in accordance with ISO 7637 Extended ambient temperature range (40 Cto+125 C) 3. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit 1 V supply voltage on pin BAT all operating modes 5.5 - 27 V BAT 2 I supply current on pin BAT LH sleep, Sleep and -45 65 A BAT Limp home mode V = 8.1 V to 27 V BAT V voltage on pin LIN DC value 27 - +40 V LIN 3 T virtual junction temperature 40 - +150 C vj V electrostatic discharge voltage human body model 8- +8 kV ESD on pins LIN, BAT, C1, C2 and C3 C=100 pF R=1.5k 1 Valid for the UJA1023T/2R04/C for the UJA1023T/2R04, V = 6.5 V to 27 V. BAT 2 All outputs turned off, LIN recessive, V selected. th1 3 Junction temperature in accordance with IEC60747-1. An alternative definition of T =T +P R , vj amb th(j-a) where R is a fixed value to be used for calculating T . The rating for T limits the allowable th(j-a) vj vj combinations of power dissipation (P) and ambient temperature (T ). amb UJA1023 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 17 August 2010 2 of 49