XC7SET125GV NXP

XC7SET125 Bus buffer/line driver 3-state Rev. 2 7 December 2015 Product data sheet 1. General description XC7SET125 is a high-speed Si-gate CMOS devices. It provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH at OE causes the output to assume a high-impedance OFF-state. 2. Features and benefits Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: HBM JESD22-A114E: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version XC7SET125GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm XC7SET125GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 XC7SET125GM 40 C to +125 C XSON6 plastic extremely thin small outline package no SOT886 leads 6 terminals body 1 1.45 0.5 mm XC7SET125GF 40 C to +125 C XSON6 plastic extremely thin small outline package SOT891 no leads 6 terminals body 1 1 0.5 mmXC7SET125 NXP Semiconductors Bus buffer/line driver 3-state 4. Marking Table 2. Marking codes 1 Type number Marking XC7SET125GW gM XC7SET125GV g25 XC7SET125GM gM XC7SET125GF gM 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram AY 4 2 Y A 2 4 1 OE 1 EN OE mna118 mna119 mna120 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning XC7SET125 XC7SET125 OE 1 6 V CC XC7SET125 OE 1 5 V OE 1 6 V CC CC A 2 5 n.c. A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 3 4 GND Y 001aak127 001aak128 001aak126 Transparent top view Transparent top view Fig 4. Pin configuration Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 SOT353-1 and SOT753 XC7SET125 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2 7 December 2015 2 of 15