74AC521 74ACT521 8-Bit Identity Comparator November 1988 Revised March 2005 74AC521 74ACT521 8-Bit Identity Comparator General Description Features The AC/ACT521 is an expandable 8-bit comparator. It com- I reduced by 50% CC pares two words of up to eight bits each and provides a Compares two 8-bit words in 6.5 ns typ LOW output when the two words match bit for bit. The Expandable to any word length expansion input I also serves as an active LOW enable A B 20-pin package input. Outputs source/sink 24 mA ACT521 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC521SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC521SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC521MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC521PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT521SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT521SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT521MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT521PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering table. Pb-Free package per JEDEC J-STD-020B. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A A Word A Inputs 0 7 B B Word B Inputs 0 7 T Expansion or Enable Input A B O Identity Output A B FACT is a trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS009964 www.fairchildsemi.comTruth Table Logic Diagram Inputs Outputs I A, B O A B A B L A B (Note 1) L L A z % H H A B (Note 1) H H A z % H H HIGH Voltage Level L LOW Voltage Level Note 1: A B , A B , A B , etc. 0 0 1 1 2 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Applications Ripple Expansion Parallel Expansion www.fairchildsemi.com 2 74AC521 74ACT521