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This literature is subject to all applicable copyright laws and is not for resale in any manner.74LCX38 Low Voltage Quad 2-Input NAND Gate (Open Drain) with 5V Tolerant Inputs October 1995 Revised February 2005 74LCX38 Low Voltage Quad 2-Input NAND Gate (Open Drain) with 5V Tolerant Inputs General Description Features The LCX38 contains four 2-input open drain NAND gates. 5V tolerant inputs The inputs tolerate voltages up to 7V allowing the interface 2.3V to 3.6V V specifications provided CC of 5V systems to 3V systems. 5.0 ns t max (V 3.3V), 10 PA I max PD CC CC The 74LCX38 is fabricated with advanced CMOS technol- Power down high impedance inputs and outputs ogy to achieve high speed operation while maintaining CMOS low power dissipation. 24 mA output drive (V 3.0V) CC Implements proprietary noise/EMI reduction circuitry Latch-up performance exceeds 500 mA ESD performance: Human body model 2000V Machine model 150V Ordering Code: Package Order Number Package Description Number 74LCX38M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX38MX NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow (Note 1) 74LCX38SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX38MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX38MTCX NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: NL indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A , B Inputs n n O Outputs n 2005 Fairchild Semiconductor Corporation DS012574 www.fairchildsemi.com