74LVC573A Low-Voltage CMOS Octal Transparent Latch With 5 VTolerant Inputs and Outputs (3State, NonInverting) www.onsemi.com The 74LVC573A is a high performance, noninverting octal MARKING transparent latch operating from a 1.2 to 3.6 V supply. High impedance DIAGRAM TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise 20 performance. A V specification of 5.5 V allows 74LVC573A inputs I LCX TSSOP20 to be safely driven from 5 V devices. 573A 20 DT SUFFIX ALYW The 74LVC573A contains 8 Dtype latches with 3state outputs. CASE 948E 1 When the Latch Enable (LE) input is HIGH, data on the Dn inputs 1 enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE A = Assembly Location is LOW, the latches store the information that was present on the D L, WL = Wafer Lot inputs a setup time preceding the HIGHtoLOW transition of LE. Y, YY = Year The 3state standard outputs are controlled by the Output Enable (OE) W, WW = Work Week input. When OE is LOW, the standard outputs are enabled. When OE G or = PbFree Package is HIGH, the standard outputs are in the high impedance state, but this (Note: Microdot may be in either location) does not interfere with new data entering into the latches. Features ORDERING INFORMATION Designed for 1.2 to 3.6 V V Operation CC See detailed ordering and shipping information on page 8 of 5 V Tolerant Interface Capability With 5 V TTL Logic this data sheet. Supports Live Insertion and Withdrawal I Specification Guarantees High Impedance When V = 0 V OFF CC 24 mA Output Sink and Source Capability Near Zero Static Supply Current in all Three Logic States (10 A) Substantially Reduces System Power Requirements ESD Performance: Human Body Model >2000 V Machine Model >200 V These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: September, 2015 Rev. 1 74LVC373A/D74LVC573A 1 OE 11 LE 19 LE O0 2 Q D0 D V O0 O1 O2 O3 O4 O5 O6 O7 LE CC 20 19 18 17 16 15 14 13 12 11 18 LE O1 3 Q D1 D 17 LE 4 O2 Q D2 D 1 2 3 4567 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 16 LE 5 O3 Q Figure 1. Pinout (Top View) D3 D 15 LE 6 O4 Q PIN NAMES D4 D Pins Function OE Output Enable Input 14 LE 7 O5 Q LE Latch Enable Input D5 D D0D7 Data Inputs O0O7 3State Latch Outputs 13 LE 8 O6 Q D6 D 12 LE 9 O7 Q D7 D Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE LE Dn On Operating Mode L H H H Transparent (Latch Disabled) Read Latch L H L L L L h H Latched (Latch Enabled) Read Latch L L l L L L X NC Hold Read Latch H L X Z Hold Disabled Outputs H H H Z Transparent (Latch Disabled) Disabled Outputs H H L Z H L h Z Latched (Latch Enabled) Disabled Outputs H L l Z H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition NC = No Change, State Prior to the Latch Enable HightoLow Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For I Reasons DO NOT FLOAT Inputs CC www.onsemi.com 2