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This literature is subject to all applicable copyright laws and is not for resale in any manner.74LVX161284 Low Voltage IEEE 161284 Translating Transceiver January 1999 Revised June 2005 74LVX161284 Low Voltage IEEE 161284 Translating Transceiver General Description Features The LVX161284 contains eight bidirectional data buffers Supports IEEE 1284 Level 1 and Level 2 signaling and eleven control/status buffers to implement a full standards for bidirectional parallel communications IEEE 1284 compliant interface. The device supports the between personal computers and printing peripherals IEEE 1284 standard and is intended to be used in an Translation capability allows outputs on the cable side to Extended Capabilities Port mode (ECP). The pinout allows interface with 5V signals for easy connection from the Peripheral (A-side) to the All inputs have hysteresis to provide noise margin Host (cable side). B and Y output resistance optimized to drive external Outputs on the cable side can be configured to be either cable open drain or high drive (r 14 mA) and are connected to a B and Y outputs in high impedance mode during power separate power supply pin (V -cable) to allow these out- CC down puts to be driven by a higher supply voltage than the A- Inputs and outputs on cable side have internal pull-up side. The pull-up and pull-down series termination resis- resistors tance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) Flow-through pin configuration allows easy interface and outputs on the cable side contain internal pull-up resis- between the Peripheral and Host tors connected to the V -cable supply to provide proper CC Replaces the function of two (2) 74ACT1284 devices termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A A /B B transceiver 1 8 1 8 pins. Ordering Code Order Number Package Number Package Description 74LVX161284MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LVX161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Pin Descriptions Pin Names Description HD High Drive Enable Input (Active HIGH) DIR Direction Control Input A A Inputs or Outputs 1 8 B B Inputs or Outputs 1 8 A A Inputs 9 13 Y Y Outputs 9 13 A A Outputs 14 17 C C Inputs 14 17 PLH Peripheral Logic HIGH Input IN PLH Peripheral Logic HIGH Output HLH Host Logic HIGH Input IN HLH Host Logic HIGH Output 2005 Fairchild Semiconductor Corporation DS500202 www.fairchildsemi.com