CM1235 Small Footprint ESD Clamp Array for High Speed Data Line Protection Product Description CM1235 Figure 1. Block Diagram ESD Protection Architecture The signal line leading the connector to the ASIC routes Conceptually, an ESD protection device performs the through the CM1235 chip which provides 100 matched following actions upon an ESD strike discharge into a differential channel characteristic impedance that helps protected ASIC (see Figure 2): optimize 100 load impedance applications such as the 1. When an ESD potential is applied to the system HDMI high speed data lines. under test (contact or airdischarge), Kirchoffs NOTE: When each of the channels are used individually Current Law (KCL) dictates that the Electrical for singleended signal lines protection, the Overstress (EOS) currents will immediately divide individual channel provides 50 characteristic throughout the circuit, based on the dynamic impedance matching. impedance of each path. The load impedance matching feature of the CM1235 helps to simplify system designers PCB layout 2. Ideally, the classic shunt ESD clamp will switch considerations in impedance matching and also eliminates within 1 ns to a lowimpedance path and return associated passive components. the majority of the EOS current to the chassis The route through the architecture enables the CM1235 to shield/reference ground. In actuality, if the ESD provide matched impedance for the signal path between the components response time (t ) is slower CLAMP connector and the ASIC. Besides this function, this circuit than the ASIC it is protecting, or if the Dynamic arrangement also changes the way the parasitic inductance Clamping Resistance (R ) is not significantly DYN interacts with the ESD protection circuit and helps reduce lower than the ASICs I/O cell circuitry, then the the I current to the ASIC. RESIDUAL ASIC will have to absorb a large amount of the EOS energy, and be more likely to fail. 3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and be ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, since it can then affect signal integrity or subsequent protection capability. (This is known as multistrike capability.) Figure 2. Standard ESD Protection Device Block Diagram