DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear May 2007 DM74ALS174, DM74ALS175 tm Hex/Quad D-Type Flip-Flops with Clear Features General Description Advanced oxide-isolated ion-implanted Schottky These positive-edge-triggered flip-flops utilize TTL TTL process circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) Pin and functional compatible with LS family version features complementary outputs from each counterpart flip-flop. Typical clock frequency maximum is 80MHz Information at the D inputs meeting the setup time Switching performance guaranteed over full requirements is transferred to the Q outputs on the temperature and V supply range CC positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Ordering Information Ordering Package Code Number Package Description DM74ALS174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering number. 1986 Fairchild Semiconductor Corporation www.fairchildsemi.com DM74ALS174, DM74ALS175 Rev. 1.2DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear Connection Diagrams DM74ALS174 DM74ALS175 1986 Fairchild Semiconductor Corporation www.fairchildsemi.com DM74ALS174, DM74ALS175 Rev. 1.2 2