DATA SHEET www.onsemi.com Gate Drivers, High-Speed, WDFN8 3x3, 0.65P CASE 511CD Low-Side, Dual 4-A 1 SOIC8 8 FAN3223/FAN3224/FAN3225 CASE 751EB 1 Description The FAN322325 family of dual 4 A gate drivers is designed to MARKING DIAGRAMS drive N channel enhancement mode MOSFETs in low-side 8 switching applications by providing high peak current pulses during XXXXX the short switching intervals. The driver is available with either TTL XXXXX XXXXX or CMOS input thresholds. Internal circuitry provides an AYWW ALYW undervoltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers 1 feature matched internal propagation delays between A and B WDFN8 SOIC8 channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting A = Assembly Lot Code L = Wafer Lot two drivers in parallel to effectively double the current capability Y = Year driving a single MOSFET. W = Work Week The FAN322X drivers incorporate MillerDrive architecture for = PbFree Package the final output stage. This bipolarMOSFET combination provides (Note: Microdot may be in either location) high current during the Miller plateau stage of the MOSFET turnon / *This information is generic. Please refer to device turn off process to minimize switching loss, while providing data sheet for actual part marking. railtorail voltage swing and reverse current capability. PbFree indicator, G or microdot , The FAN3223 offers two inverting drivers and the FAN3224 offers may or may not be present. two noninverting drivers. Each device has dual independent enable pins that default to ON if not connected. In the FAN3225, each channel has dual inputs of opposite polarity, which allows configuration as ORDERING INFORMATION See detailed ordering and shipping information on page 20 of noninverting or inverting with an optional enable function using the this data sheet. second input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the power MOSFET OFF. Applications SwitchMode Power Supplies Features High-Efficiency MOSFET Switching IndustryStandard Pinouts Synchronous Rectifier Circuits 4.5 V to 18 V Operating Range DC-to-DC Converters 5 A Peak Sink/Source at V = 12 V DD Motor Control 4.3 A Sink / 2.8 A Source at V = 6 V OUT Choice of TTL or CMOS Input Thresholds Related Resources Three Versions of Dual Independent Drivers: AN6069 Application Review and Dual Inverting + Enable (FAN3223) Comparative Evaluation of LowSide Gate Dual NonInverting + Enable (FAN3224) Drivers DualInputs (FAN3225) Internal Resistors Turn Driver Off If No Inputs MillerDrive Technology 12 ns / 9 ns Typical Rise/Fall Times (2.2 nF Load) Under 20 ns Typical Propagation Delay Matched within 1 ns to the Other Channel Double Current Capability by Paralleling Channels 8Lead 3x3 mm MLP, 8Lead SOIC Package Rated from 40C to +125C Ambient These are PbFree Devices Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: August, 2021 Rev. 3 FAN3223/DFAN3223/FAN3224/FAN3225 PACKAGE OUTLINES 1 8 1 8 2 7 2 7 3 6 3 6 4 5 4 5 Figure 1. 3x3 mm MLP8 (Top View) Figure 2. SOIC8 (Top View) THERMAL CHARACTERISTICS (Note 1) L JT JA JB JT Package (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Unit 8Lead 3x3 mm Molded Leadless Package (MLP) 1.2 64 42 2.8 0.7 C/W 8Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the MLP8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2