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This literature is subject to all applicable copyright laws and is not for resale in any manner.FAN3278 30V PMOS-NMOS Bridge Driver July 2012 FAN3278 30V PMOS-NMOS Bridge Driver Description Features The FAN3278 dual 1.5A gate driver is optimized to drive 8V to 27V Optimum Operating Range a high-side P-channel MOSFET and a low-side Drives High-Side PMOS and Low-Side NMOS in N-channel MOSFET in motor control applications Motor Control or Buck Step-Down Applications operating from a voltage rail up to 27V. Internal circuitry limits the voltage applied to the gates of the external Output Drive-Voltage Magnitude Limited: < 13V MOSFETs to 13V maximum. The driver has TTL input for V up to 30V DD thresholds and provides buffer and level translation from Biases Each Load Device OFF with a 100k logic inputs. Internal circuitry prevents the output Resistor when V Below Operating Level DD switching devices from operating if the V supply DD voltage is below the IC operation level. Internal 100k Low-Voltage TTL Input Thresholds resistors bias the non-inverting output LOW and the Peak Gate Drives at 12V: +1.5A Sink, -1.0A Source inverting output to V to keep the external MOSFETs DD Internal Resistors Hold Driver Off When off during startup intervals when logic control signals No Inputs Present may not be present. 8-Lead SOIC Package The FAN3278 driver incorporates MOSFET devices for the final output stage, providing high current throughout Rated from 40C to +125C Ambient the MOSFET turn-on / turn-off transition to minimize switching loss. The internal gate-drive regulators Applications provide optimum gate-drive voltage when operating from a rail of 8V to 27V. The FAN3278 can be driven Motor Control with PMOS / NMOS Half-Bridge from a voltage rail of less than 8V however, its gate Configuration drive current is reduced. Buck Converters with High-Side PMOS Device The FAN3278 has two independent ENABLE pins that 100% Duty Cycle Operation Possible default to ON if not connected. If the ENABLE pin for Logic-Controlled Load Circuits with High-Side non-inverting channel A is pulled LOW, OUTA is forced PMOS Switch LOW. If the ENABLE pin for inverting channel B is pulled LOW, OUTB is forced HIGH. If an input is left unconnected, internal resistors bias the inputs such that the external MOSFETs are OFF. Figure 1. Typical Application 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3278 Rev. 1.0.1