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This literature is subject to all applicable copyright laws and is not for resale in any manner.FAN5903 Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs June 2013 FAN5903 Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Features Description 2.7 V to 5.5 V Input Voltage Range FAN5903 is a high-efficiency, low-noise, synchronous, step-down, DC-DC converter designed for powering V Range from 0.4 V to 3.5 V (or V ) OUT IN 3G / 3.5G / 4G RF Power Amplifiers (PAs) in handsets Small Form Factor Inductor and other mobile applications. o 2012 470 nH or 540 nH for Minimal PCB Area The output voltage may be dynamically varied from o 2520 1.0 H for Higher Efficiency 0.40 V to 3.50 V, proportional to an analog input V , CON ranging from 0.16 V to 1.40 V provided by an external Bypass Dropout at 500 mA, 60 mV Typical DAC. This allows the PA to be supplied with the voltage 100% Duty Cycle for Low Dropout Operation that enables maximum power-added efficiency. Input Under-Voltage Lockout / Thermal Shutdown An integrated bypass FET automatically switches on when battery voltage drops close to the desired output 1.34 mm x 1.29 mm, 9-Bump, 0.4 mm-Pitch, voltage (V = V - 200 mV). The DC-DC switches OUT BAT Wafer-Level Chip-Scale Package (WLCSP) back to Synchronous Mode when the voltage dropout 3 MHz / 6 MHz Selectable Switching Frequency to exceeds 375 mV. The integrated bypass FET is also Facilitate System Optimization enabled when V is nominally greater than to 1.5 V. CON High-Efficiency PFM Operation at Low Power The FAN5903 offers fast transition times, enabling changes to the output voltage in less than 10 s for Sleep Mode for Very Low I Operation Q power transitions. Moreover, a Current-Mode control Up to 96% Efficient Synchronous Operation at loop with fast transient response ensures excellent line High-Power Conditions and load regulation. 10 s Output Voltage Step Response for Early Light-load efficiency is optimized by operating in PFM Power Loop Settling Mode for load currents typically less than 100 mA. The switching frequency may be set to 3 MHz or Applications 6 MHz, enabling further optimization of system performance. The FAN5903 typically uses a single, Dynamic Supply Bias for 3G/3.5G and 4G PAs small-form-factor inductor of 470 nH or 540 nH. Power Supply for WCDMA/LTE PAs Efficiency may be further optimized using a 1.0 H inductor when running at 3 MHz. Resources When output regulation is not required, the FAN5903 may be placed in Sleep Mode by setting V nominally CON For more information or a full copy of this datasheet, to 50 mV. This ensures a very low I (<70 A) while Q please contact a Fairchild representative. enabling a fast return to output regulation. The FAN5903 enables significant current reduction and increased talk time and is available in a 1.34 mm x 1.29 mm, 9-bump, 0.40 mm-pitch, WLCSP package. Ordering Information Operating Part Number Package Packing Method Temperature Range 1.34 mm x 1.29 mm, 9-bump, 0.4 mm Pitch, FAN5903UCX -40 to +85C Tape and Reel Wafer-Level Chip-Scale Package (WLCSP) 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5903 Rev. 1.0.9