FAN5910 Multi-Mode Buck Converter with LDO Assist for GSM / EDGE, 3G/3.5G and 4G PAs Description The FAN5910 is a high efficiency, low noise, synchronous, www.onsemi.com step down, DC DC converter optimized for powering Radio Frequency (RF) Power Amplifiers (PAs) in handsets and other mobile applications. Load currents up to 2.5 A are allowed, which enables GSM / EDGE, 3G/3.5G, and 4G platforms under very poor VSWR conditions. 12KK WLCSP XYZ The output voltage may be dynamically adjusted from 0.40 V to 16 BUMP 3.60 V, proportional to an analog input voltage V ranging from CON CASE 567SD 0.16 V to 1.44 V, optimizing power added efficiency. Fast transition 12 = Alphanumeric Device Code times are achieved, allowing excellent interslot settling. (See Ordering Information for An integrated LDO is automatically enabled under heavy load specific marking) conditions or when the battery voltage and voltage drop across the KK = Lot Run Number DC DC PMOS device are within a set range of the desired output X = Alphabetical Year Code voltage. This LDOassist feature supports heavy load currents under Y= 2weeks Date Code Z = Assembly Plant Code the most stringent battery and V conditions while maintaining SWR high efficiency, low dropout, and superior spectral performance. The FAN5910 DC DC operates in PWM Mode with a 2.9 MHz switching frequency and supports a single, small formfactor inductor ranging from 1.0 H to 2.2 H. In addition, PFM operation is allowed at low load currents for output voltages below 1.5 V to maximize efficiency. PFM operation can be disabled by setting MODE pin to LOW. When output regulation is not required, the FAN5910 may 2.9 MHz PWM Mode be placed in Sleep Mode by setting V below 100 mV CON Sleep Mode for ~50 A Standby Current Consumption nominally. This ensures a very low I (<50 A) while Q Forced PWM Mode enabling a fast return to output regulation. Up to 95% Efficient Synchronous Operation in High FAN5910 is available in a low profile, small form factor, Power Conditions 16 bump, WaferLevel ChipScale Package (WLCSP) that 2.9 MHz PWMOnly Mode is 1.615 mm x 1.615 mm. Only three external components Auto PFM/PWM Mode are required: two 0402 capacitors and one 2016 inductor. 2.9 MHz PWM Operation at High Power and PFM Features Operation at Low Power and Low Output Voltage 2 for Maximum Low Current Efficiency Solution Size < 9.52 mm 2.7 V to 5.5 V Input Voltage Range Applications V Range from 0.40 V to 3.60 V (or V ) OUT IN Dynamic Supply Bias for Polar or Linear GSM / EDGE Single, Small FormFactor Inductor PAs and 3G/3.5G and 4G PAs 29 m Integrated LDO Dynamic Supply Bias for GSM / EDGE Quad Band 100% Duty Cycle for LowDropout Operation Amplifiers for Mobile Handsets and Data Cards Input UnderVoltage Lockout / Thermal Shutdown 1.615 mm x 1.615 mm, 16Bump, 0.4 mm Pitch WLCSP Semiconductor Components Industries, LLC, 2018 1 Publication Order Number: March, 2019 Rev. 0 FAN5910/DFAN5910 ORDERING INFORMATION Temperature Device Range Marking Part Number Output Voltage Package Packing FAN5910UCX 0.4 V to PVIN 40C to +85C 1.615 mm x 1.615 mm, 16Bump 0.4 mm Pitch, Tape and Reel LJ WaferLevel ChipScale Package (WLCSP) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Block Diagrams 0.4V to3.6V PVIN FB up to2.5A for V >3.7V BAT 220pF 10 F VOUT Up to3A in PVIN Bypass Mode VOUT 1.5 H VOUT AVIN V IN SW .7V to 2 FAN5910 5.5V SW BPEN 4.7 F 6.8 pF 10 F 10 F PGND PGND PGND MODE EN From External AGND VCON DAC Figure 1. Typical Application 1. The three 4.7 F capacitors include the FAN5910 output capacitor and PA bypass capacitors. 2. Regulator requires only one 4.7 F the V bus should not exceed 14 F capacitance over DC bias and temperature. OUT PVIN VOUT LDO FB Assist AVIN Positive Current Limit AGND PFM/PWM VCON Controller SW 3 MHz BPEN Oscillator MODE to PWM Controller Negative EN Current Limit PGND Figure 2. Simplified Block Diagram www.onsemi.com 2