FL73282MX ON Semiconductor

DATA SHEET www.onsemi.com Half-Bridge Gate Driver FL73282 SOIC8 CASE 751EB Description The FL73282, a monolithic half bridge gatedrive IC, can drive MOSFETs and IGBTs that operate up to +900V. onsemis MARKING DIAGRAM highvoltage process and common mode noise canceling technique provides stable operation of the highside driver under highdV /dt S noise circumstances. An advanced levelshift circuit allows highside Y&E&Z&2&K gate driver operation up to V = 9.8 V (typical) for V = 15 V. S BS FL73282 The UVLO circuits for both channels prevent malfunction when V CC MB or V is lower than the specified threshold voltage. Output drivers BS typically source/sink 350 mA / 650 mA, respectively, which is suitable for all kinds of half and fullbridge inverters. FL73282MB = Device Code Features Y = onsemi Logo Floating Channel for Bootstrap Operation to +900 V &E = Designates Space Typically 350 mA / 650 mA Sourcing/Sinking &Z = Assembly Plant Code &2 = 2Digit Date Code Format Current Driving Capability for Both Channels &K = 2Digits Lot Run Traceability Code CommonMode dv/dt Noise Canceling Circuit Extended Allowable Negative V Swing to 9.8 V S ORDERING INFORMATION for Signal Propagation at V = V = 15 V CC BS See detailed ordering and shipping information on page 13 of V & V Supply Range from 10 V to 20 V CC BS this data sheet. UVLO Functions for Both Channels Matched Propagation Delay Below 50 ns Builtin 170 ns DeadTime Output in Phase with Input Signal Applications Fluorescent Lamp Ballast HID Ballast SMPS Motor Driver General Purpose Half Bridge Topology Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: November, 2021 Rev. 2 FL73282/DDRIVER DRIVER PULSE GENERATOR FL73282 APPLICATION DIAGRAM Up to 900 V 15 V D R BOOT BOOT 1 8 V V CC B Q1 R1 HO 2 7 HIN HIN R2 C BOOT V 3 LIN 6 LIN S Q2 C1 R3 COM LO 4 5 Load R4 Figure 1. Application Circuit for Half Bridge Topology BLOCK DIAGRAM 8 V B UVLO 7 HO R R NOISE CANCELLER S Q 6 V S HS(ON/OFF) SCHMITT TRIGGER INPUT HIN 2 UVLO 1 V CC SHOOT THROUGH PREVENTION LIN 3 LS(ON/OFF) DELAY 5 LO DEADTIME=170ns 4 COM Figure 2. Functional Block Diagram www.onsemi.com 2