FUSB303B Autonomous USB Type-C Port Controller with 2 I C and GPIO Control FUSB303B Description www.onsemi.com The FUSB303B device is a fully autonomous USB TypeC controller optimized for 15 W or less applications. The FUSB303B offers CC logic detection for Source Port role, Sink Port role, DRP, and accessory detection support, as well as Dead Battery support as defined in USB C specifications. The FUSB303B features 2 configurable address I C access to support multiple ports per system QFN12 or it can operate autonomously configured by just pins. The CASE 722AG FUSB303B features ultralow power during operation, and an ultrathin, 12Lead QFN package. MARKING DIAGRAM Features Fully Autonomous USBC Port Controller UNKK Supports Latest TypeC Specification Release 1.3 XYZ Source, Sink, and DRP Port role Configuration with Optional Accessory Support 1 Try.SRC and Try.SNK modes for Preferring Source Role or Sink UN = FUSB303B Device Code Role Respectively KK = Lot Trace Code V Operating Range, 2.855.5 V = Pin 1 Identifier DD XY = Two Digit Date Code Typical Low Power Operation: I < 10 A CC Z = Assembly Plant Code 2 GPIO and I C Configuration Max 28 V DC Tolerance on ID, VBUS DET, CC1 and CC2 ORDERING INFORMATION Dead Battery Support (Sink Port role when No Power Applied) See detailed ordering and shipping information on page 17 of 4 kV HBM ESD Protection for Connector Pins this data sheet. Small Packaging, 12 Lead QFN (1.6 mm 1.6 mm 0.375 mm) Applications Smartphones Tablets Laptops Accessoires Industrial Power Banks Semiconductor Components Industries, LLC, 2020 1 Publication Order Number: April, 2020 Rev. 1 FUSB303B/DFUSB303B BOOT PMID (debug boot signals) SYSTEM TEST SW FAN54511 3.2A Charger BAT VBUS VBUS 4.7F 1.8V VDDIO SYS ID PORT/ DEBUG N ID VBUS DET VDD FUSB303B INT N / INT N OUT3 Processor SRC, SRC+Acc, CC1 SDA / CC Switches, (I2C master 2 SNK, SNK+Acc, I C section) OUT1 I(Rp)/Rd & SDA Slave DRP & DRP+Acc CC2 Comparators Block State Machines SCL / OUT2 SCL VDD Osc BG EN N ADDR/ 900k GND ORIENT 2 Figure 1. Typical I C Application BOOT PMID (debug boot signals) SW SYSTEM TEST FAN54511 3.2A Charger BAT VBUS VBUS SYS GPIO 4 Internal pullup PORT/ DEBUG N ID VBUS DET If no processor available, VDD tie ID to gate of Source PMOSFET, EN N to GND FUSB303B and leave SDA/OUT1 & SCL/OUT2 unconnected. INT N / OUT3 SRC, SRC+Acc, CC1 SDA / CC Switches, 2 SNK, SNK+Acc, I C OUT1 I(Rp)/Rd & GPIO 1 DRP & DRP+Acc Slave CC2 Comparators Block SNK or SRC Internal pullup State Machines GPIO 1:2 =10/11: default SCL / GPIO 1:2 =01: 1.5A Processor OUT2 GPIO 1:2 =00: 3A GPIO 2 (USB2.0/3.1 PHY Internal pullup section) VDD Osc BG SS Tx1/Rx1 GPIO 3 EN N ADDR/ GND ORIENT SS Tx2/Rx2 S FUSB340 (USB 3.1 USB 2.0 SS Tx/Rx &3.1 2:1 MUX) PHY Figure 2. Typical GPIO Application www.onsemi.com 2 IO Buffers & IO Buffers & Controller Controller USB Type C Connector USB TypeC Connector