HCPL0600, HCPL0601, HCPL0611, HCPL0637, HCPL0638, HCPL0639 High Speed-10 MBit/s Logic Gate Optocouplers www.onsemi.com Single Channel: HCPL0600, HCPL0601, HCPL0611 Dual Channel: HCPL0637, HCPL0638, HCPL0639 Description The HCPL06XX optocouplers consist of an AlGaAS LED, SOIC8 optically coupled to a very high speed integrated photodetector logic CASE 751DZ gate with a strobable output (single channel devices). The devices are housed in a compact smalloutline package. This output features an open collector, thereby permitting wired OR outputs. The HCPL0600, MARKING DIAGRAM HCPL0601 and HCPL0611 output consists of bipolar transistors on a bipolar process while the HCPL0637, HCPL0638, and HCPL0639 1 output consists of bipolar transistors on a CMOS process for reduced power consumption. The coupled parameters are guaranteed over the 2 ON 600 temperature range of 40C to +85C. An internal noise shield provides superior common mode rejection. 6 V X YY S Features Compact SO8 Package 34 5 Very High Speed10 MBit/s Superior CMR 1. ON = ON Semiconductor Logo 2. 600 = Device Number Logic Gate Output 3. V = VDE mark indicates Strobable Output (Single Channel Devices) DIN EN/IEC6074752 approval (Note: Only appears on parts Wired ORopen Collector ordered with VDE option See Ordering Information Table) Safety and Regulatory Approvals 4. X = OneDigit Year Code, e.g. 3 UL1577, 3750 VAC for 1 min RMS 5. YY = Two Digit Work Week Ranging DIN EN/IEC6074755, 565 V Peak Working Insulation Voltage from 01 to 53 6. S = Assembly Package Code Typical Applications Ground Loop Elimination ORDERING INFORMATION LSTTL to TTL, LSTTL or 5volt CMOS See detailed ordering and shipping information on page 13 of Line Receiver, Data Transmission this data sheet. Data Multiplexing Switching Power Supplies Pulse Transformer Replacement Computerperipheral Interface Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: October, 2019 Rev. 2 HCPL0639/DHCPL0600, HCPL0601, HCPL0611, HCPL0637, HCPL0638, HCPL0639 N/C 1 8 V + 1 8 V CC CC V F1 + 2 7 V 2 7 V E 01 V F 3 6 V 3 6 V O 02 V F2 N/C 4 5 GND + 4 5 GND Figure 1. Singlechannel Circuit Drawing Figure 2. Dualchannel Circuit Drawing (HCPL0600, HCPL0601 and HCPL0611) (HCPL0637, HCPL0638 and HCPL0639) TRUTH TABLE (Positive Logic) Input Enable Output H H L L H H H L H L L H H* NC* L* L* NC* H* *Dual channel devices or single channel devices with pin 7 not connected. A 0.1 F bypass capacitor must be connected between pins 8 and 5. (See Note 2) www.onsemi.com 2