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Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic range, www.onsemi.com excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 120 frames per second. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. Other features include low dark current, negligible lag, and low smear. The sensor shares common pinout and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to support multiple members of this sensor family. Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Figure 1. KAI01050 Interline CCD Architecture Interline CCD, Progressive Scan Image Sensor Total Number of Pixels 1084 (H) 1064 (V) Number of Effective Pixels 1040 (H) 1040 (V) Features Number of Active Pixels 1024 (H) 1024 (V) Pixel Size 5.5 m (H) 5.5 m (V) Color or Monochrome Configurations Active Image Size 5.632 mm (H) 5.632 mm (V) Progressive Scan Readout 7.96 mm (diagonal), 1/2 Optical Format Flexible Readout Architecture Aspect Ratio 1:1 High Frame Rate Number of Outputs 1, 2, or 4 High Sensitivity Charge Capacity 20,000 electrons Low Noise Architecture Output Sensitivity 34 V/e Excellent Smear Performance Quantum Efficiency Package Pin Reserved for Device Monochrome (ABA) 44% R, G, B (FBA) 31%, 37%, 38% Identification R, G, B (CBA) 29%, 37%, 39% Read Noise (f = 40 MHz) 12 e rms Applications Dark Current Industrial Imaging Photodiode / VCCD 7 / 140 e /s Medical Imaging Dark Current Doubling Temp Photodiode / VCCD 7C / 9C Security Dynamic Range 64 dB Charge Transfer Efficiency 0.999999 ORDERING INFORMATION Blooming Suppression > 300 X See detailed ordering and shipping information on page 2 of this data sheet. Smear 100 dB Image Lag < 10 electrons Maximum Pixel Clock Speed 40 MHz Maximum Frame Rate Quad / Dual / Single Output 120 / 60 / 30 fps Package 68 Pin PGA 64 Pin CLCC Cover Glass AR Coated, 2-Sides NOTE: All Parameters are specified at T = 40C unless otherwise noted. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: July, 2015 Rev. 5 KAI01050/D