LC75806PT 1/4 and 1/3-Duty LCD Driver with Key Input Function Overview www.onsemi.com The LC75806PT is 1/4 duty and 1/3 duty LCD display driver that can directly drive up to 304 segments and can control up to 9 general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features Key input function for up to 30 keys (A key scan is performed only when a key is pressed) 1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data. Capable of driving up to 304 segments using 1/4 duty and up to 231 TQFP100 14x14 / TQFP100 segments using 1/3 duty. Switching between key scan output and segment output can be controlled from serial data. The key scan operation enabled/disabled state can be controlled from serial data. Switching between segment output port and general-purpose output port can be controlled from serial data. Switching between general-purpose output port, clock output port, and segment output port can be controlled from serial data. (Up to 9 general-purpose output ports and up to one clock output port) Serial data I/O supports CCB* format communication with the system controller. (Support 3.3 V and 5 V operation) Sleep mode and all segments off functions that are controlled from serial data. The frame frequency of the common and segment output waveforms can be controlled from serial data. Switching between RC oscillator operating mode and external clock operationg mode can be controlled from serial data. Direct display of display data without the use of a decoder provides high generality. Built-in display contrast adjustment circuit. Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. RES pin provided for forcibly initializing the IC internal circuits. * Computer Control Bus (CCB) is an ON Semiconductors original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 36 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number : June 2017 - Rev. 1 LC75806PT/D LC75806PT Specifications Absolute Maximum Ratings at Ta = 25 C, V = 0 V SS Parameter Symbol Conditions Ratings Unit V max V Maximum supply voltage 0.3 to +7.0 V DD DD V 1 CE, CL, DI, RES 0.3 to +7.0 IN Input voltage V V 2 OSC, TEST, V 1, V 2, KI1 to KI5 0.3 to V +0.3 IN DD DD DD V 1 DO 0.3 to +7.0 OUT Output voltage V OSC, S1 to S77, COM1 to COM4, KS1 to KS6, V 2 0.3 to V +0.3 OUT DD P1 to P9 I 1 S1 to S77 300 OUT A I 2 COM1 to COM4 3 OUT Output current I 3 KS1 to KS6 1 mA OUT I 4 OUT P1 to P9 5 Allowable power dissipation Pd max 200 mW Ta = 85C Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +85C, V = 0 V SS Ratings Parameter Symbol Conditions Unit min typ max V V Supply voltage 4.5 6.0 V DD DD V1 V 1 2/3V0 V 0 DD DD DD DD Input voltage *1 V V2 V 2 1/3V0 V 0 DD DD DD DD V 1 0.4V 6.0 IH CE, CL, DI, RES DD V 2 0.6V V Input high level voltage KI1 to KI5 V IH DD DD V 3 0.4V V OSC: External clock operating mode IH DD DD V 1 0.2V 0 IL CE, CL, DI, RES DD V 2 0.2V Input low level voltage KI1 to KI5 0 V IL DD V 3 0.2V OSC: External clock operating mode 0 IL DD Recommended external R OSC: RC oscillation operating mode 39 k OSC resistor for RC oscillation Recommended external C OSC: RC oscillation operating mode 1000 pF OSC capacitor for RC oscillation Guaranteed range of RC f OSC OSC: RC oscillation operating mode 19 38 76 kHz oscillation External clock operating OSC: External clock operating mode f 10 38 76 kHz CK frequency Figure4 OSC: External clock operating mode D External clock duty cycle 30 50 70 % CK Figure4 t Data setup time CL, DI Figure2 , Figure3 160 ns ds t Data hold time CL, DI Figure2 , Figure3 160 ns dh t CE wait time CE, CL Figure2 , Figure3 160 ns cp t CE setup time CE, CL Figure2 , Figure3 160 ns cs t CE hold time CE, CL Figure2 , Figure3 160 ns ch t High level clock pulse width CL Figure2 , Figure3 160 ns H t Low level clock pulse width CL Figure2 , Figure3 160 ns L t Rise time CE, CL, DI Figure2 , Figure3 160 ns r t Fall time CE, CL, DI Figure2 , Figure3 160 ns f DO R =4.7k C =10pF *2 PU L t DO output deley time 1.5 s dc Figure2 , Figure3 DO R =4.7k C =10pF *2 PU L t DO rise time 1.5 s dr Figure2 , Figure3 Note: *1. V 0=0.70V to V DD DD DD *2. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistorR and the load capacitance C . PU L Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2