OrdeOrdering numbering numberr : ENA1956A : ENA1956A LC87FBK08A CMOS IC 8K-byte FROM and 256-byte RAM integrated LC87FBK08A Minimum Instruction Cycle Time 250ns (12MHz at V =2.7V to 5.5V) DD Ports Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units 12 (P1n, P20, P21, P70, CF2/XT2) Ports I/O direction can be designated in 4-bit units 8 (P0n) Dedicated oscillator ports/input ports 1 (CF1/XT1) Reset pin 1 ( ) RES Power pins 2 (V 1, V 1) SS DD Timers Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes SIO SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) AD Converter: 12 bits/8 bits 8 channels 12 bits/8 bits AD converter resolution selectable Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN) Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function Capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. Capable generating the source clock for the subclock Watchdog Timer Capable generating an internal reset on an overflow of a timer running on the low-speed RC oscillator clock or subclock. Operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a count value held). No.A1956-2/28