M MC74VHC1GT04 Inverting Buffer / CMOS Logic Level Shifter LSTTLCompatible Inputs The MC74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation www.onsemi.com similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. MARKING The internal circuit is composed of three stages, including a buffer DIAGRAMS output which provides high noise immunity and stable output. The device input is compatible with TTLtype input thresholds and 5 the output has a full 5 V CMOS level output swing. The input protection SC88A 5 circuitry on this device allows overvoltage tolerance on the input, VK M DF SUFFIX CASE 419A allowing the device to be used as a logiclevel translator from 3 V 1 CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V 1 CMOS Logic while operating at the highvoltage power supply. The MC74VHC1GT04 input structure provides protection when 5 voltages up to 7.0 V are applied, regardless of the supply voltage. This TSOP5 5 VK M allows the MC74VHC1GT04 to be used to interface 5 V circuits to DT SUFFIX CASE 483 3 V circuits. The output structures also provide protection 1 1 when V = 0 V. These input and output structures help prevent CC device destruction caused by supply voltage input/output voltage VK = Device Code mismatch, battery backup, hot insertion, etc. M = Date Code* = PbFree Package Features (Note: Microdot may be in either location) High Speed: t = 3.8 ns (Typ) at V = 5 V PD CC *Date Code orientation and/or position may vary Low Power Dissipation: I = 1 A (Max) at T = 25C CC A depending upon manufacturing location. TTLCompatible Inputs: V = 0.8 V V = 2 V IL IH CMOSCompatible Outputs: V > 0.8 V V < 0.1 V Load OH CC OL CC PIN ASSIGNMENT Power Down Protection Provided on Inputs and Outputs 1 NC Balanced Propagation Delays 2 IN A Pin and Function Compatible with Other Standard Logic Families 3 GND Chip Complexity: FETs = 105 Equivalent Gates = 26 4 OUT Y NLV Prefix for Automotive and Other Applications Requiring 5V Unique Site and Control Change Requirements AECQ100 CC Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS FUNCTION TABLE Compliant A Input Y Output NC 1 5 V CC L H H L IN A 2 GND 34 OUT Y ORDERING INFORMATION Figure 1. Pinout (Top View) See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 1 IN A OUT Y Figure 2. Logic Symbol Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 18 MC74VHC1GT04/DMC74VHC1GT04 MAXIMUM RATINGS Symbol Characteristics Value Unit V DC Supply Voltage 0.5 to +7.0 V CC V DC Input Voltage 0.5 to +7.0 V IN V DC Output Voltage V = 0 0.5 to 7.0 V OUT CC High or Low State 0.5 to V + 0.5 CC I Input Diode Current 20 mA IK I Output Diode Current V < GND V > V +20 mA OK OUT OUT CC I DC Output Current, per Pin +25 mA OUT I DC Supply Current, V and GND +50 mA CC CC P Power dissipation in still air SC88A, TSOP5 200 mW D Thermal resistance SC88A, TSOP5 333 C/W JA T Lead temperature, 1 mm from case for 10 s 260 C L T Junction temperature under bias +150 C J T Storage temperature 65 to +150 C stg V ESD Withstand Voltage Human Body Model (Note 1) 2000 V ESD Machine Model (Note 2) 200 Charged Device Model (Note 3) N/A I Latchup Performance Above V and Below GND at 125C (Note 4) 100 mA Latchup CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22A114A 2. Tested to EIA/JESD22A115A 3. Tested to JESD22C101A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit V DC Supply Voltage 3.0 5.5 V CC V DC Input Voltage 0.0 5.5 V IN V DC Output Voltage V = 0 0.0 5.5 V OUT CC High or Low State 0.0 V CC T Operating Temperature Range 55 +125 C A t , t Input Rise and Fall Time V = 3.3 V 0.3 V 0 100 ns/V r f CC V = 5.0 V 0.5 V 0 20 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES Junction FAILURE RATE OF PLASTIC = CERAMIC Temperature C UNTIL INTERMETALLICS OCCUR Time, Hours Time, Years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 1 110 79,600 9.4 120 37,000 4.2 1 10 100 1000 130 17,800 2.0 TIME, YEARS 140 8,900 1.0 Figure 3. Failure Rate vs. Time Junction Temperature www.onsemi.com 2 NORMALIZED FAILURE RATE T = 130C J T = 120C J T = 110 C J T = 100C J T = 90 J C T = 80 J C