MC100LVELT23DR2G ON Semiconductor

MC100LVELT23 3.3 VDual Differential LVPECL/LVDS to LVTTL Translator Description www.onsemi.com The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead 8 package and the dual gate design of the LVELT23 makes it ideal for 8 1 applications which require the translation of a clock and a data signal. 1 1 The LVELT23 is available in only the ECL 100K standard. Since SOIC8 NB TSSOP8 DFN8 there are no LVPECL outputs or an external V reference, the BB D SUFFIX DT SUFFIX MN SUFFIX LVELT23 does not require both ECL standard versions. The LVPECL CASE 75107 CASE 948R02 CASE 506AA inputs are differential. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a V of +3.3 V. CC MARKING DIAGRAMS* Features 2.0 ns Typical Propagation Delay 8 8 Maximum Frequency > 180 MHz KVT23 KR23 Differential LVPECL Inputs ALYW ALYW PECL Mode Operating Range:V = 3.0 V to 3.8 V CC 14 1 1 with GND = 0 V SOIC8 TSSOP8 DFN8 24 mA LVTTL Outputs Flow Through Pinouts A = Assembly Location L = Wafer Lot Internal Pulldown and Pullup Resistors Y = Year These Devices are Pb-Free, Halogen Free and are RoHS Compliant W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100LVELT23DG SOIC8 NB 98 Units/Tube (Pb-Free) MC100LVELT23DR2G SOIC8 NB 2500/Tape & Reel (Pb-Free) MC100LVELT23DTG TSSOP8 100 Units/Tube (Pb-Free) MC100LVELT23DTRG TSSOP8 2500/Tape & Reel (Pb-Free) MC100LVELT23MNRG DFN8 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 19 MC100LVELT23/D 4J M MC100LVELT23 Table 1. PIN DESCRIPTION D0 1 8 V CC Pin Function Q0, Q1 LVTTL Outputs D0*, D1* Differential LVPECL Inputs D0 2 7 Q0 D0*, D1* V Positive Supply CC GND Ground LVPECL LVTTL EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal con- D1 3 6 Q1 duit. Electrically connect to the most neg- ative supply (GND) or leave unconnec- ted, floating open. ** Pins will default to V /2 when left open. CC D145 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 k Internal Input Pullup Resistor 50 k ESD Protection Human Body Model > 1500 V Machine Model > 100 V CDM > 2000 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 91 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information. www.onsemi.com 2