MC10EP56DTG ON Semiconductor

3.3 V/5 VECL Dual Differential 2:1 Multiplexer MC10EP56, MC100EP56 Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The www.onsemi.com differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple V pins are BB provided. The V pin, an internally generated voltage supply, is available to BB this device only. For singleended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB SOIC20 TSSOP20 QFN20 and V via a 0.01 F capacitor and limit current sourcing or sinking CC DW SUFFIX DT SUFFIX MN SUFFIX to 0.5 mA. When not used, V should be left open. CASE 751D CASE 948R BB CASE 485E The device features both individual and common select inputs to address both data path and random logic applications. MARKING DIAGRAMS* The 100 Series contains temperature compensation. 20 20 1 XXXX Features XXXX MC100EP56 EP56 EP56 360 ps Typical Propagation Delays AWLYYWWG ALYW ALYW Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: V = 3.0 V to 5.5 V 1 CC with V = 0 V EE XXXX = MC10 or 100 NECL Mode Operating Range: V = 0 V A = Assembly Location CC WL, L = Wafer Lot with V = 3.0 V to 5.5 V EE YY, Y = Year Open Input Default State WW, W = Work Week Safety Clamp on Inputs G, = PbFree Package Separate and Common Select (Note: Microdot may be in either location) Q Output Will Default LOW with Inputs Open or at V EE *For additional marking information, refer to Application Note AND8002/D. V Outputs BB These Devices are PbFree and are RoHS Compliant ORDERING INFORMATION Device Package Shipping MC10EP56DTG TSSOP20 75 Units / Tube (PbFree) MC10EP56DTR2G TSSOP20 2500 / (PbFree) Tape & Reel MC10EP56MNG QFN20 92 Units / Tube (PbFree) SOIC20 MC100EP56DWG 38 Units / Tube (PbFree) MC100EP56DTG TSSOP20 75 Units / Tube (PbFree) MC100EP56DTR2G TSSOP20 2500 / (PbFree) Tape & Reel MC100EP56MNG QFN20 92 Units / Tube (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2021 Rev. 18 MC10EP56/DMC10EP56, MC100EP56 Table 1. PIN DESCRIPTION PIN FUNCTION D0a* D1a* ECL Input Data a V Q0 Q0 SEL0 V Q1 Q1 V CC SEL1 CC EE D0a* D1a* ECL Input Data a Invert 20 19 18 17 16 15 14 13 12 11 D0b* D1b* ECL Input Data b D0b* D1b* ECL Input Data b Invert SEL0* SEL1* ECL Indiv. Select Input COM SEL* ECL Common Select Input V , V Output Reference Voltage BB0 BB1 10 1 0 Q0 Q1 ECL True Outputs Q0 Q1 ECL Inverted Outputs V Positive Supply CC V Negative Supply EE EP Exposed Pad 1 2 3 4 5 678 9 10 D0a D0a V D0b D0b D1a D1a V D1b D1b * Pins will default LOW when left open. BBO BB1 Warning: All V and V pins must be externally connected CC EE Table 2. TRUTH TABLE to Power Supply to guarantee proper operation. Q0, Q1, Figure 1. 20 Lead Package (Top View) and Logic SEL0 SEL1 COM SEL Q0 Q1 Diagram X X H a a L L L b b L H L b a H H L a a H L L a b Exposed Pad D0a D0a V Q0 Q0 CC 20 19 18 17 16 V 1 15 SEL0 BB0 D0b 2 14 COM SEL D0b MC10/100EP56 3 13 SEL1 4 D1a 12 V CC D1a 5 11 Q1 67 8 9 10 V D1b D1b V Q1 BB1 EE NOTE: The Exposed Pad (EP) on package bottom must be attached to a heatsinking conduit. The Exposed Pad may only be electrically connected to V . EE Figure 1. QFN20 Pinout (Top View) www.onsemi.com 2 COM SEL