MC74HC165A 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register HighPerformance SiliconGate CMOS www.onsemi.com The MC74HC165A is identical in pinout to the LS165. The device MARKING inputs are compatible with standard CMOS outputs with pullup DIAGRAMS resistors, they are compatible with LSTTL outputs. 16 This device is an 8bit shift register with complementary outputs PDIP16 from the last stage. Data may be loaded into the register either in MC74HC165AN 16 N SUFFIX parallel or in serial form. When the Serial Shift/Parallel Load input is AWLYYWWG CASE 648 low, the data is loaded asynchronously in parallel. When the Serial 1 Shift/Parallel Load input is high, the data is loaded serially on the 1 rising edge of either Clock or Clock Inhibit (see the Function Table). 16 The 2input NOR clock may be used either by combining two SOIC16 HC165AG independent clock sources or by designating one of the clock inputs to D SUFFIX 16 AWLYWW act as a clock inhibit. CASE 751B 1 1 Features 16 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL TSSOP16 HC 16 165A DT SUFFIX Operating Voltage Range: 2.0 to 6.0 V ALYW CASE 948F 1 Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices 1 In Compliance with the Requirements Defined by JEDEC Standard QFN16 165A No. 7 A MN SUFFIX ALYW CASE 485AW Chip Complexity: 286 FETs or 71.5 Equivalent Gates 1 NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 A = Assembly Lo- cation Qualified and PPAP Capable L, WL = Wafer Lot These Devices are PbFree, Halogen Free and are RoHS Compliant Y, YY = Year W, WW = Work Week G or = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 Rev. 9 MC74HC165A/DMC74HC165A SERIAL SHIFT/ SERIAL SHIFT/ PARALLEL LOAD V CC 1 16 V CC PARALLEL LOAD 116 CLOCK 2 15 CLOCK INHIBIT CLOCK215 CLOCK INHIBIT E 3 14 D E314 D F 4 13 C F413 C GND G 5 12 B G512 B H 6 11 A H611 A Q 7 10 S H A Q710 S H A 89 GND 8 9 Q H GND Q H Figure 1. Pin Assignments 11 A 12 B 9 13 Q H SERIAL C PARALLEL 14 DATA D 7 DATA OUTPUTS Q 3 H E INPUTS 4 F 5 G 6 H PIN 16 = V SERIAL CC 10 S PIN 8 = GND DATA A INPUT 1 SERIAL SHIFT/ PARALLEL LOAD 2 CLOCK 15 CLOCK INHIBIT Figure 2. Logic Diagram FUNCTION TABLE Inputs Internal Stages Output Serial Shift/ Clock Parallel Load Inhibit Clock S A H Q Q Q A A B H Operation L X X X a h a b h Asynchronous Parallel Load H L L X L Q Q An Gn Serial Shift via Clock H L H X H Q Q An Gn H L L X L Q Q An Gn Serial Shift via Clock Inhibit H L H X H Q Q An Gn H X H X X No Change Inhibited Clock H H X X X H L L X X No Change No Clock X = dont care Q Q = Data shifted from the preceding stage An Gn www.onsemi.com 2