MC74HC595ADTG ON Semiconductor

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs HighPerformance SiliconGate CMOS www.onsemi.com MC74HC595A The MC74HC595A consists of an 8bit shift register and an 8bit Dtype latch with threestate parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous SOIC16 TSSOP16 reset for the shift register. D SUFFIX DT SUFFIX CASE 751B CASE 948F The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. Features 1 Output Drive Capability: 15 LSTTL Loads QFN16 MN SUFFIX Outputs Directly Interface to CMOS, NMOS, and TTL CASE 485AW Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices MARKING DIAGRAMS 16 In Compliance with the Requirements Defined by JEDEC 16 HC Standard No. 7 A 595A HC595AG Chip Complexity: 328 FETs or 82 Equivalent Gates ALYW AWLYWW Improvements over HC595 1 1 Improved Propagation Delays SOIC16 50% Lower Quiescent Power TSSOP16 Improved Input Noise and Latchup Immunity 595A NLV Prefix for Automotive and Other Applications Requiring ALYW Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable QFN16* These Devices are PbFree, Halogen Free and are RoHS Compliant *V595A marking used for NLV74HC595AMN1TWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G, = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2021 Rev. 25 MC74HC595A/DMC74HC595A Q V B CC Q 1 16 V B CC 116 Q 2 15 Q C A Q215 Q C A Q 3 14 A D 314 Q A D Q 4 13 OUTPUT ENABLE E 413 OUTPUT ENABLE Q E GND Q 5 12 LATCH CLOCK F Q512 LATCH CLOCK F Q 6 11 SHIFT CLOCK G Q611 SHIFT CLOCK G Q 7 10 RESET H Q710 RESET H 89 GND 8 9 SQ H GND SQ H SOIC, TSSOP QFN Figure 1. Pin Assignments LOGIC DIAGRAM SERIAL 14 15 DATA A Q A 1 INPUT Q B 2 Q C 3 PARALLEL Q D DATA 4 Q SHIFT E OUTPUTS LATCH 5 REGISTER Q F 6 Q G 7 Q H SHIFT 11 CLOCK SERIAL 10 9 RESET SQ DATA H OUTPUT LATCH 12 CLOCK V = PIN 16 CC 13 OUTPUT GND = PIN 8 ENABLE www.onsemi.com 2