MC74VHC132 Quad 2-Input NAND Schmitt Trigger The MC74VHC132 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky www.onsemi.com TTL while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC74VHC00, MARKING but the inputs have hysteresis and, with its Schmitt trigger function, DIAGRAMS the VHC132 can be used as a line receiver which will receive slow input signals. 14 The internal circuit is composed of three stages, including a buffer SOIC14 VHC132G D SUFFIX output which provides high noise immunity and stable output. The AWLYWW CASE 751A 1 inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V 1 systems to 3.0 V systems. 14 Features VHC High Speed: t = 4.9 ns (Typ) at V = 5.0 V TSSOP14 PD CC 132 DT SUFFIX Low Power Dissipation: I = 2 A (Max) at T = 25C CC A ALYW CASE 948G 1 High Noise Immunity: V = V = 28% V NIH NIL CC 1 Power Down Protection Provided on Inputs A = Assembly Location Balanced Propagation Delays WL, L = Wafer Lot Designed for 2.0 V to 5.5 V Operating Range Y = Year WW, W = Work Week Low Noise: V = 0.8 V (Max) OLP G or = PbFree Package Pin and Function Compatible with Other Standard Logic Families (Note: Microdot may be in either location) Latchup Performance Exceeds 300mA ESD Performance: Human Body Model > 2000 V FUNCTION TABLE Machine Model > 200 V Inputs Output Chip Complexity: 72 FETs or 18 Equivalent Gates AB Y These Devices are PbFree and are RoHS Compliant LL H LH H V B4 A4 Y4 B3 A3 Y3 HL H CC HH L 14 13 12 11 10 9 8 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 1 2 3 4 567 A1 B1 Y1 A2 B2 Y2 GND (Top View) Figure 1. Pinout: 14Lead Packages Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2017 Rev. 7 MC74VHC132/DMC74VHC132 1 9 A1 A3 3 8 Y1 Y3 2 10 B1 B3 4 12 A2 A4 6 11 Y2 Y4 5 13 B2 B4 Figure 2. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage 0.5 to +7.0 V CC due to high static voltages or electric V DC Input Voltage 0.5 to +7.0 V in fields. However, precautions must be taken to avoid applications of any V DC Output Voltage 0.5 to V +0.5 V out CC voltage higher than maximum rated I Input Diode Current 20 mA voltages to this highimpedance cir- IK cuit. For proper operation, V and in I Output Diode Current 20 mA OK V should be constrained to the out range GND (V or V ) V . I DC Output Current, per Pin 25 mA in out CC out Unused inputs must always be I DC Supply Current, V and GND Pins 50 mA CC CC tied to an appropriate logic voltage level (e.g., either GND or V ). P Power Dissipation in Still Air, SOIC Packages 500 mW CC D Unused outputs must be left open. TSSOP Package 450 T Storage Temperature 65 to +150 C stg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOIC Packages: 7 mW/C from 65 to 125C TSSOP Package: 6.1 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage 2.0 5.5 V CC V DC Input Voltage 0 5.5 V in V DC Output Voltage 0 V V out CC T Operating Temperature, All Package Types 55 + 125 C A Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2