MM74HC157M ON Semiconductor

MM74HC157 Quad 2-Input Multiplexer September 1983 Revised February 1999 MM74HC157 Quad 2-Input Multiplexer The 74HC logic family is functionally as well as pin-out General Description compatible with the standard 74LS logic family. All inputs The MM74HC157 high speed Quad 2-to-1 Line data selec- are protected from damage due to static discharge by inter- tor/Multiplexers utilizes advanced silicon-gate CMOS tech- nal diode clamps to V and ground. CC nology. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, Features as well as the ability to drive 10 LS-TTL loads. Typical propagation delay: 14 ns data to any output This device consists of four 2-input digital multiplexers with common select and STROBE inputs. When the STROBE Wide power supply range: 26V input is at logical 0 the four outputs assume the values as Low power supply quiescent current: 80 A maximum selected from the inputs. When the STROBE input is at a (74HC Series) logical 1 the outputs assume logical 0. Fan-out of 10 LS-TTL loads Low input current: 1 A maximum Ordering Code: Order Number Package Number Package Description MM74HC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Function Table Inputs Output Pin Assignments for DIP, SOIC, SOP and TSSOP Strobe Select A B Y HX XX L LL LX L LL HX H LH XL L LH XH H H = HIGH Level, L = LOW Level X = Irrelevant Top View 1999 Fairchild Semiconductor Corporation DS005314.prf www.fairchildsemi.comLogic Diagram www.fairchildsemi.com 2 MM74HC157