NBC12430, NBC12430A 3.3V/5VProgrammable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12430, NBC12430A +3.3 or 5.0 V 1 1 MHz F PLL V REF CC with 16 MHz Crystal PHASE 16 DETECTOR +3.3 or 5.0 V 3 XTAL SEL VCO 21, 25 2 V CC FREF EXT 24 F 9 BIT M N OUT 4 2 23 XTAL1 COUNTER (1, 2, 4, 8) F OUT 400 800 MHz 10 20MHz OSC 20 5 TEST XTAL2 LATCH LATCH 6 OE 28 S LOAD LATCH 7 P LOAD 01 01 27 S DATA 2BIT SR 3BIT SR 9BIT SR 26 S CLOCK 8 16 17, 18 22, 19 9 2 M 8:0 N 1:0 Figure 1. Block Diagram (PLCC28) Table 1. Output Division Table 2. XTAL SEL And OE N 1:0 Output Division Input 0 1 0 0 2 XTAL SEL FREF EXT XTAL 0 1 4 OE Outputs Disabled Outputs Enabled 1 0 8 1 1 1