TinyLogic UHS D-Type Latch with 3-STATE Output NC7SZ373 Description The NC7SZ373 is a single positive edgetriggered Dtype CMOS Lach with 3STATE output from ON Semiconductors Ultra High www.onsemi.com Speed Series of TinyLogic in the space saving SC70 6lead package. The device is fabricated with advanced CMOS technology to achieve MARKING ultra high speed with high output drive while maintaining low static DIAGRAMS power dissipation over a very broad V operating range. The device CC is specified to operate over the 1.65 V to 5.5 V V range. The inputs CC SIP6 1.45x1.0 D4KK and output are high impedance when V is 0 V. Inputs tolerate CC CASE 127EB XYZ voltages up to 5.5 V independent of V operating voltage. The latch CC appears transparent to the data when Latch Enable (LE) is HIGH. Pin 1 When LE is LOW, the data that meets the setup time is latched. The output tolerates voltages above V in the 3STATE condition. 6 CC SC88 Features Z73M CASE 419B02 Space Saving SC88 6Lead Package Ultra Small MicroPak Leadless Package 1 Ultra High Speed: t = 2.6 ns Typ into 50 pF at 5 V V PD CC D4, Z73 = Specific Device Code High Output Drive: 24 mA at 3 V V CC KK = 2Digit Lot Run Traceability Code Broad V Operating Range: 1.65 V to 5.5 V CC XY = 2Digit Date Code Format Matches the Performance of LCX when Operated at 3.3 V V Z = Assembly Plant Code CC M = Date Code* Power Down High Impedance Inputs / Output = PbFree Package Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation (Note: Microdot may be in either location) Patented Noise / EMI Reduction Circuitry Implemented *Date Code orientation and/or position may These Devices are PbFree, Halogen Free/BFR Free and are RoHS vary depending upon manufacturing location. Compliant IEEC / IEC ORDERING INFORMATION OE See detailed ordering, marking and shipping information in the package dimensions section on page 7 of this data sheet. LE D Q Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2004 1 Publication Order Number: January, 2021 Rev. 2 NC7SZ373/DNC7SZ373 Connection Diagrams LE 1 LE 6 OE LE 1 6 OE GND 2 5 V CC GND 2 5 V DQ CC DQ3 4 D 3 4 Q Figure 2. SC88 (Top View) Figure 4. MicroPak (Top Through View) (Top View) AAA Pin One AAA = Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin 1 Orientation PIN DESCRIPTIONS FUNCTION TABLE Pin Name Description Inputs Output D Data Input LE D OE Q CP Latch Enable Input H L L L OE Output Enable Input H H L H Q Latch Output L X L Q n 1 X X H Z H = HIGH Logic Level X = Immaterial L = LOW Logic Level Z = HIGH Impedance Q = Previous state prior to HIGHtoLOW transition of latch n 1 enable www.onsemi.com 2
