NC7WZ38K8X ON Semiconductor

TinyLogic UHS Dual 2-Input NAND Gate (Open Drain Output) NC7WZ38 Description www.onsemi.com The NC7WZ38 is a dual 2Input NAND Gate with open drain output stage from ON Semiconductors Ultra High Speed Series of MARKING TinyLogic. The device is fabricated with advanced CMOS technology DIAGRAMS to achieve ultra high speed with high output drive while maintaining low static power dissipation over a very broad V operating range. CC UQFN8 The device is specified to operate over the 1.65 V to 5.5 V V range. U5KK CC 1.6X1.6, 0.5P XYZ The inputs and output are high impedance when V is 0 V. Inputs CC CASE 523AY tolerate voltages up to 5.5 V independent of V operating voltage. CC The open drain output stage will tolerate voltages up to 5.5 V independent of V when in the high impedance state. CC Features WZ38 US8 Space Saving US8 Surface Mount Package ALYW CASE 846AN MicroPak PbFree Leadless Package Open Drain Output Stage for OR Tied Applications Ultra High Speed: t 2.2 ns Typ. into 50 pF at 5 V V PD CC High Output Sink Drive: 24 mA at 3 V V CC U5, WZ38 = Specific Device Code Broad V Operating Range: 1.65 V to 5.5 V CC KK = 2Digit Lot Run Traceability Code Matches the Performance of LCX when Operated at 3.3 V V CC XY = 2Digit Date Code Format Power Down High Impedance Inputs / Output Z = Assembly Plant Code A = Assembly Site Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation L = Wafer Lot Number Patented Noise / EMI Reduction Circuitry Implemented YW = Assembly Start Week These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. IEEE/IEC A 1 & Y 1 B 1 A 2 & Y 2 B 2 Figure 1. Logic Symbol Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: October, 2020 Rev. 2 NC7WZ38/DNC7WZ38 Connection Diagram A 1 8 V A B Y 1 CC 1 1 2 7 6 5 B 2 7 Y 1 1 V 8 4 GND CC Y 3 6 B 2 2 GND45 A 2 1 2 3 Y B A 1 2 2 Figure 2. Connection Diagram (Top View) Figure 4. Pad Assignments for MicroPak (Top Thru View) (Top View) AAA Pin One AAA represents Product Code Top Mark see ordering code NOTE: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Figure 3. Pin One Orientation Diagram PIN DESCRIPTIONS FUNCTION TABLE (Y = AB) Pin Names Description Inputs Output A , B Inputs A B Y n n Y Output L L *H n L H *H H L *H H H L H = HIGH Logic Level L = LOW Logic Level *H = HIGH Impedance Output State (Open Drain) www.onsemi.com 2