DATA SHEET www.onsemi.com Bluetooth 5.2 System-in-Package (SiP) RSL10 SIP SIP51 8x6 CASE 127EY Introduction RSL10 SystemInPackage (RSL10 SIP) is a complete solution that provides the easiest way to integrate the industrys lowest power Bluetooth Low Energy technology into a wireless application. XXXXX The RSL10 SIP features an onboard antenna, RSL10 radio SoC, AWLYWW and all necessary passive components in one package to help minimize overall system size. Already fully qualified to FCC, CE, and other (SIP51) regulatory standards RSL10 SIP removes the need for additional antenna design considerations or RF certifications. XXXXXX = Specific Device Code A = Assembly Location Key Features WL = Wafer Lot Fully Certified: Y = Year WW = Work Week Bluetooth 5.2 G or = PbFree Package QDID Declaration ID FCC, CE, IC, MIC, KCC ORDERING INFORMATION Industrys Lowest Power: Device Package Shipping Peak Rx Current = 5.6 mA (1.25 V VBAT) Peak Rx Current = 3.0 mA (3 V VBAT) NCHRSL10 SIP51 2500 / 101S51ACG (PbFree) Tape & Reel Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT) Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT) For information on tape and reel specifications, including part orientation and tape sizes, please Deep Sleep Current Consumption (1.25 V VBAT): refer to our Tape and Reel Packaging Specification Deep Sleep, IO Wakeup: 50 nA Brochure, BRD8011/D. Deep Sleep, 8 kB RAM Retention: 300 nA Current Consumption (3 V VBAT): Deep Sleep, IO Wakeup: 25 nA Deep Sleep, 8 kB RAM Retention: 100 nA EEMBC ULPMark Core Profile (3 V): 1090 EEMBC ULPMark Core Profile (2.1 V): 1360 Advanced Wireless: Bluetooth 5.2 Certified with LE 2Mbit PHY (High Speed), as well as Backwards Compatibility and Support for Earlier Bluetooth Low Energy Specifications Supports FOTA (Firmware OverTheAir) Updates Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): 93 dB Transmitting Power: 17 to +6 dBm Range up to 100 Meters Other Key Features Arm Cortex M3 Processor Clocked at up to 48 MHz Supply Voltage Range: 1.1 3.3 V 384 kB of Flash Memory 76 kB of Program Memory 88 kB of Data Memory Semiconductor Components Industries, LLC, 2018 1 Publication Order Number: January, 2022 Rev. 4 RSL10SIP/DRSL10 SIP FEATURES 2 Arm CortexM3 Processor: A 32bit core for realtime Highly Configurable Interfaces: I C, UART, two SPI applications, specifically developed to enable interfaces, PCM interface, multiple GPIOs. It also highperformance lowcost platforms for a broad range supports a digital microphone interface (DMIC) and an of lowpower applications. output driver (OD). LPDSP32: A 32 bit Dual Harvard DSP core that Flexible Clocking Scheme: RSL10 must be clocked efficiently supports intensive signal processing from the XTAL/PLL of the radio frontend at 48 MHz applications. Various codecs are available to customers when transmitting or receiving RF traffic. When RSL10 through libraries that are included in RSL10s is not transmitting/receiving RF traffic, it can run off the development tools. 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low frequency RTC Radio Frequency FrontEnd: Based on a 2.4 GHz RF clock at 32 kHz can also be used in Deep Sleep Mode. It transceiver, the RFFE implements the physical layer of can be sourced from either the internal XTAL, the RC the Bluetooth Low Energy technology standard and other oscillator, or a digital input pad. proprietary or custom protocols. Diverse Memory Architecture: 76kB of SRAM Protocol Baseband Hardware: Bluetooth 5.2 certified program memory (4 kB of which is PROM containing the and includes support for a 2 Mbps RF link and custom chip bootup program, and is thus unavailable to the user) protocol options. The RSL10 baseband stack is and 88 kB of SRAM data memory are available. A total supplemented by support structures that enable of 384 kB of flash is available to store the Bluetooth stack implementation of onsemi and customer designed and other applications. custom protocols. The Arm CortexM3 processor can execute from SRAM HighlyIntegrated SoC: The dualcore architecture is and/or flash. complemented by highefficiency power management Security: AES128 encryption hardware block for custom units, oscillators, flash and RAM memories, a DMA secure algorithms and code protection with authenticated controller, along with a full complement of peripherals debug port access (JTAG lock) and interfaces. UltraLow Power Consumption Application Deep Sleep Mode: RSL10 can be put into a Deep Sleep Examples: Mode when no operations are required. Various Deep Low Duty Cycle Advertising: IDD 1.1 A for Sleep Mode configurations are available, including: advertising at all three channels at 5 second intervals IO wakeup configuration. The power consumption VBAT 3 V, DCDC converter enabled. in deep sleep mode is 50 nA (1.25 V VBAT). Embedded 32 kHz oscillator running with interrupts RoHS Compliant Device from timer or external pin. The total current drain is 90 nA (1.25 V VBAT). As above with 8 kB RAM data retention. The total current drain is 300 nA (1.25 V VBAT). The DCDC converter can be used in buck mode or LDO mode during Sleep Mode, depending on VBAT voltage. Standby Mode: Can be used to reduce the average power consumption for offduty cycle operation, ranging typically from a few ms to a few hundreds of ms. The typical chip power consumption is 30 A in Standby Mode. MultiProtocol Support: Using the flexibility provided by LPDSP32, the Arm CortexM3 processor, and the RF frontend proprietary protocols and other custom protocols are supported. Flexible Supply Voltage: RSL10 integrates high efficiency power regulators and has a VBAT range of 1.1 to 3.3 V. www.onsemi.com 2