DATA SHEET www.onsemi.com LDO Regulator - Ultra-Low Noise, High PSRR, RF and WLCSP4 Analog Circuits CASE 567JZ 450 mA MARKING DIAGRAM NCP148 X A1 The NCP148 is a linear regulator capable of supplying 450 mA output current. Designed to meet the requirements of RF and analog X = Specific Device Code circuits, the NCP148 device provides low noise, high PSRR, low M = Date Code quiescent current, and very good load/line transients. The NCP148 offers softstart function with optimized slew rate control to use in camera module. The device is designed to work with a 1 F input and a PIN CONNECTIONS 1 F output ceramic capacitor. It is available in ultrasmall 0.35P, IN OUT 0.64 mm x 0.64 mm Chip Scale Package (CSP). Features A2 A1 Operating Input Voltage Range: 1.9 V to 5.5 V Available in Fixed Voltage Option: 1.8 V to 5.14 V B1 B2 Optimized Startup Slew Rate for Camera Sensor EN GND 2% Accuracy Over Load/Temperature (Top View) Low Quiescent Current Typ. 55 A Standby Current: Typ. 0.1 A Very Low Dropout: 150 mV at 450 mA ORDERING INFORMATION See detailed ordering and shipping information on page 12 of Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz this data sheet. Ultra Low Noise: 10 V RMS Stable with a 1 F Small Case Size Ceramic Capacitors Available in WLCSP4 0.64 mm x 0.64 mm x 0.33 mm CASE 567JZ These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Typical Applications Camera Modules Batterypowered Equipment Smartphones, Tablets Cameras, DVRs, STB and Camcorders V V OUT IN IN OUT NCP148 C EN IN C OUT 1 F ON 1 F Ceramic Ceramic GND OFF Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 3 NCP148/DNCP148 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description A1 IN Input voltage supply pin A2 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. B1 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN B2 GND Common ground connection EPAD Expose pad should be tied to ground plane for better power dissipation ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 to 6 V IN Output Voltage V 0.3 to V + 0.3, max. 6 V OUT IN Chip Enable Input V 0.3 to 6 V CE Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22A114 ESD Machine Model tested per EIA/JESD22 A115 Latchup Current Maximum Rating tested per JEDEC standard: JESD78. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, CSP4 (Note 3) R 108 C/W JA Thermal Resistance, JunctiontoAir 3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51 7 www.onsemi.com 2