NCP171AMX280275TCG ON Semiconductor

LDO Regulator - Ultra-Low Iq, Dual Power Mode 50 nA, 80 mA NCP171 The NCP171 is a Dual mode LDO offering up to 80 mA in Active Mode and as low as 50 nA of Iq in Low Power Mode. The Dual Mode www.onsemi.com function is selectable with the ECO pin allowing for dynamic switching between Active and Low Power Modes, ideal in long life battery powered applications. The output Voltage in Low Power mode can be lowered by an internally factory programmed value ranging 50 mV, 100 mV, 150 mV 1 or 200 mV with respect to the nominal output voltage in Active Mode. XDFN4 1.2x1.2 This feature further lowers the application consumption in sleep mode. AM SUFFIX The NCP171 is in the SLIQ (Super Low Iq) LDO family and is CASE 711BC available in small XDFN4 1.2 x 1.2 package. Features MARKING DIAGRAM Operating Input Voltage Range: 1.7 V to 5.5 V Output Voltage Range: 0.6 V to 3.3 V (50 mV steps) XXM Low Power Mode / Active Mode Externally Controlled by ECO pin 1 Internally Factory Programmable Output Voltage Offset for Low XX = Specific Device Code Power/Active Mode to 50 mV, 100 mV, 150 mV, 200 mV M = Date Code Quiescent Current of 50 nA at No Load, (Low Power mode) Maximum Current 80 mA in Active Mode and 5 mA in Low Power Mode PIN CONNECTIONS Low Dropout: 41 mV Typ. at 80 mA (Vout = 3.3 V) 2% Output Voltage Accuracy in Active Mode ENA 4 3 IN High PSRR: 65 dB at 1 kHz in Active Mode Active Output Discharge for Fast Output TurnOff GND Current Limitation, Thermal Shutdown ECO 1 2 OUT Available in Small XDFN4 1.2x1.2 Package These are PbFree Devices (Top View) Typical Applications IoT ORDERING INFORMATION RFID See detailed ordering, marking and shipping information on Portable Communication Equipment page 20 of this data sheet. Consumer Electronics Figure 1. Typical Application Schematic Semiconductor Components Industries, LLC, 2018 1 Publication Order Number: December, 2019 Rev. 2 NCP171/DNCP171 Active Mode part ECO Current Limit & Thermal Shutdown Low Power part Vin Vout Active Discharge Vref Voltage Scaling ENA GND Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. XDFN4 Pin Name Description 1 ECO Low Power and Active mode control pin. Pulling this pin to ground switches the device into Low Power mode and pushing this pin to output voltage switches the device into Active mode. 2 OUT Output pin 3 IN Input pin 4 ENA Enable pin. Driving ENA above 1.2 V turns on the regulator. Driving ENA below 0.4 V puts the regulator into shutdown mode. 5(EP) GND Ground www.onsemi.com 2