NCP302LSN27T1G ON Semiconductor

DATA SHEET www.onsemi.com Voltage Detector Series MARKING DIAGRAM with Programmable Delay 5 NCP302, NCP303 TSOP5/ xxx AYW 5 SOT235 The NCP302 and NCP303 series are second generation ultralow 1 CASE 483 1 current voltage detectors that contain a programmable time delay generator. These devices are specifically designed for use as reset xxx = Specific Device Code controllers in portable microprocessor based systems where extended A = Assembly Location battery life is paramount. Y = Year Each series features a highly accurate undervoltage detector with W = Work Week hysteresis and an externally programmable time delay generator. This = PbFree Package combination of features prevents erratic system reset operation. (Note: Microdot may be in either location) The NCP302 series consists of complementary output devices that are available with either an active high or active low reset. The NCP303 series has an open drain NChannel output with an active low PIN CONNECTIONS reset output. Reset Features 1 5 C D Output Quiescent Current of 0.5 A Typical 2 Input High Accuracy Undervoltage Threshold of 2.0% Externally Programmable Time Delay Generator 3 4 N.C. Ground Wide Operating Voltage Range of 0.8 V to 10 V (Top View) Complementary or Open Drain Output Active Low or Active High Reset Specified Over the 40C to +125C Temperature Range ORDERING INFORMATION (Except for Voltage Options from 0.9 to 1.1 V) See detailed ordering and shipping information in the ordering information section on page 22 of this data sheet. NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree and are RoHS Compliant Typical Applications Microprocessor Reset Controller Low Battery Detection Power Fail Indicator Battery Backup Detection Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2021 Rev. 27 NCP302/DNCP302, NCP303 NCP303LSNxxT1 NCP302xSNxxT1 Complementary Output Configuration Open Drain Output Configuration 2 Input 2 Input 1 Reset Output R R D D 1 Reset * V V ref ref Output 3 GND5C 3 GND5C D D * Inverter for active low devices. * Buffer for active high devices. This device contains 28 active transistors. Figure 1. Representative Block Diagrams MAXIMUM RATINGS Rating Symbol Value Unit Input Power Supply Voltage (Pin 2) V 12 V in Delay Capacitor Pin Voltage (Pin 5) V 0.3 to V + 0.3 V CD in Output Voltage (Pin 1) V V OUT Complementary, NCP302 0.3 to V + 0.3 in NChannel Open Drain, NCP303 0.3 to 12 Output Current (Pin 1) (Note 2) I 70 mA OUT Thermal Resistance JunctiontoAir R 250 C/W JA Maximum Junction Temperature T +150 C J Operating Ambient Temperature Range All Voltage Options: 0.9 V to 1.1 V T 40 to +85 C A All Voltage Options: 1.2 V to 4.9 V T 40 to +125 C A Storage Temperature Range T 55 to +150 C stg Moisture Sensitivity Level MSL 1 Latchup Performance (Note 3) I mA LATCHUP Positive 200 Negative 200 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MILSTD883, Method 3015. Machine Model Method 200 V. 2. The maximum package power dissipation limit must not be exceeded. T T J(max) A P D R JA 3. Maximum ratings per JEDEC standard JESD78. www.onsemi.com 2