NCP4629HDT120T5G ON Semiconductor

NCP4629 500 mA, Wide Input Range, LDO Linear Voltage Regulator The NCP4629 is a CMOS 500 mA LDO linear voltage regulator which features a high input voltage range while maintaining a low NCP4629 VIN VOUT Vref Current Limit Short Protection CE Thermal Shutdown GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. SOT89 DPAK Pin Name Description 1 1 VIN Input pin 2 2 GND* Ground pin, all ground pins must be connected together when it is mounted on board 3 3 GND* Ground pin, all ground pins must be connected together when it is mounted on board 4 4 CE Chip enable pin (H active) 5 5 VOUT Output pin 6 GND Heatsink surface is internally connected to Pin 2 GND 6 GND Heatsink surface is internally connected to Pin 3 GND *Pin no.2 GND and pin no.3 GND of SOT89 and DPAK5 packages must be wired to the GND line when it is mounted on board. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage V 0.3 to 36 V IN Output Voltage VOUT 0.3 to VIN 36 V Chip Enable Input VCE 0.3 to VIN 36 V Power Dissipation SOT895 P 900 mW D Power Dissipation DPAK 5 1900 Junction Temperature T 40 to 150 C J Storage Temperature T 55 to 125 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Duration time = 200 ms 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Machine Model tested per AECQ100003 (EIA/JESD22A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78.