NCP51190, NCV51190 1.5A DDR Memory Termination Regulator The NCP/NCV51190 is a simple, costeffective, highspeed linear regulator designed to generate the V termination voltage rail for TT DDRI, DDRII and DDRIII memory. The regulator is capable of www.onsemi.com actively sourcing or sinking up to 1.5 A for DDRI, or up to 0.5 A for DDRII /III while regulating the output voltage to within MARKING 30 mV. DIAGRAM The output termination voltage is tightly regulated to track V = TT (V / 2) over the entire current range. DDQ 1 DFN8 The NCP/NCV51190 incorporates a highspeed differential XXM MN SUFFIX amplifier to provide ultrafast response to line and load transients. CASE 506AA 1 Other features include extremely low initial offset voltage, excellent load regulation, source/sink softstart and onchip thermal shutdown XX = Specific Device Code protection. M = Date Code The NCP/NCV51190 features the powersaving Suspend To Ram = PbFree Device (STR) function which will tristate the regulator output and lower the (Note: Microdot may be in either location) quiescent current drawn when the /SS pin is pulled low. The NCP/NCV51190 is available in a DFN8 package. PIN CONNECTION Features Generate DDR Memory Termination Voltage (V ) TT For DDRI, DDRII, DDRIII Source / Sink Currents Supports DDRI to 1.5 A, DDRII, DDRIII to 0.5 A (peak) Integrated Power MOSFETs with Thermal Protection Stable with 10 F Ceramic V Capacitor TT High Accuracy Output Voltage at FullLoad Minimal External Component Count ORDERING INFORMATION Shutdown for Standby or Suspend to RAM (STR) mode See detailed ordering, marking and shipping information in the package dimensions section on page 8 of this data sheet. Builtin Soft Start NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These are PbFree Devices Appications Desktop PCs, Notebooks, and Workstations Graphics Card DDR Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Bus Termination Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2017 Rev. 4 NCP51190/DNCP51190, NCV51190 1.5 A, DDRI /II /III TERMINATION REGULATOR Figure 1. Typical Application Schematic PIN FUNCTION DESCRIPTION NCP51190 Pin Number Pin Name Pin Function 1 PV The PV pin provides the rail voltage from where the V pin draws load current. There is a limitation CC CC TT between V and PV . The PV voltage must be less or equal to the V voltage to ensure the CC CC CC CC correct output voltage regulation. The V source current capability is dependent on PV voltage. The TT CC higher the voltage on PV , the higher the source current. CC 2 V Regulator output voltage capable of sinking and sourcing current while regulating the output rail. TT 3 GND Common Ground. 4 /SS Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V output to TT high impedance state. Logic HI = Enable, Logic LO = Shutdown. 5 V V is the V sense input. TTS TTS TT 6 V V is an output pin that provides the buffered output of the internal reference voltage equal to half of REF REF V . Two resistors dividing down the V voltage on the pin to create the regulated output voltage. DDQ DDQ 7 V The V pin is an input pin for creating the internal reference voltage to regulate V . The V volt- DDQ DDQ TT DDQ age is connected to an internal resistor divider. The central tap of resistor divider (V /2) is con- DDQ nected to the internal voltage buffer, which output is connected to V pin and the noninverting input REF of the error amplifier as the reference voltage. 8 V Power for the analog control circuitry. CC THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple PAD vias for maximum power dissipation performance. www.onsemi.com 2