NCP59749MN2ADJTBG ON Semiconductor

NCP59749 Linear Regulator - Dual-Rail, Very LowDropout, Programmable SoftStart NCP59749 Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Name QFN20 Description IN 58 Unregulated input to the device. EN 11 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. SS 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 200 s. BIAS 10 Bias input voltage for error amplifier, reference, and internal control circuits. PG 9 Power-Good (PG) is an open-drain, active-high output that indicates the status of V . When V OUT OUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When V is below this OUT threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 k to 1 M should be connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. FB 16 This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. OUT 1, 1820 Regulated output voltage. A small capacitor (total typical capacitance 2.2 F, ceramic) is needed from this pin to ground to assure stability. NC 24, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. GND 12 Ground PAD/TAB Should be soldered to the ground plane for increased thermal performance