NCP702SN18T1G ON Semiconductor

NCP702 Linear Voltage Regulator - Ultra-Low Quiescent Current, Ultra-Low Noise, LDO 200 mA NCP702 IN ENABLE THERMAL UVLO EN LOGIC SHUTDOWN MOSFET BANDGAP INTEGRATED DRIVER WITH REFERENCE SOFTSTART CURRENT LIMIT + OUT AUTO LOW POWER MODE ACTIVE EEPROM DISCHARGE EN GND Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin XDFN 6 TSOP5 Name Description 1 5 OUT Regulated output voltage pin. A small 1 F ceramic capacitor is needed from this pin to ground to assure stability. 2 4 N/C Not connected. This pin can be tied to ground to improve thermal dissipation. 3 2 GND Power supply ground. 4 3 EN Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode. 5 N/C Not connected. This pin can be tied to ground to improve thermal dissipation. 6 1 IN Input pin. It is recommended to connect a 1 F ceramic capacitor close to the device pin. Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 V to 6 V V IN Output Voltage V 0.3 V to V + 0.3 V V OUT IN Enable Input V 0.3 V to V + 0.3 V V EN IN Output Short Circuit Duration t Indefinite s SC Maximum Junction Temperature T 150 C J(MAX) Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Machine Model tested per AECQ100003 (EIA/JESD22A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78.