NCP720 350mA, Very Low Dropout Bias Rail CMOS Voltage Regulator The NCP720 is a 350 mA VLDO equipped with NMOS pass transistor and a separate bias supply voltage (V ). The device BIAS www.onsemi.com provides very stable, accurate output voltage with low noise suitable T for space constrained, noise sensitive applications. In order to MARKING optimize performance for battery operated portable applications, the DIAGRAM NCP720 features low I consumption. The WDFN6 2 mm x 2 mm Q package is optimized for use in space constrained applications. 1 WDFN6 XX M Features CASE 511BR Input Voltage Range: 0.8 V to 5.5 V Bias Voltage Range: 2.4 V to 5.5 V XX = Specific Device Code Fixed Output Voltage Device M = Date Code Output Voltage Range: 0.8 V to 2.1 V 2% Accuracy over Temperature PIN CONNECTIONS UltraLow Dropout: 110 mV typically at 350 mA Very Low Bias Input Current of Typ. 80 A OUT IN Very Low Bias Input Current in Disable Mode: Typ. 0.5 A 1 6 Low Noise, High PSRR BuiltIn SoftStart with Monotonic V Rise Thermal OUT NC GND 2 5 Pad Stable with a 2.2 F Ceramic Capacitor Available in WDFN6 2 mm x 2 mm Package EN 3 4 BIAS These are PbFree Devices Typical Applications (Top VIew) Batterypowered Equipment Smartphones, Tablets ORDERING INFORMATION Cameras, DVRs, STB and Camcorders See detailed ordering, marking and shipping information on page 8 of this data sheet. V BIAS NCP720 BIAS OUT V OUT V 1.5 V 350 mA IN IN 2.2 F EN GND V EN Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: May, 2017 Rev. 2 NCP720/DNCP720 CURRENT IN OUT LIMIT ENABLE EN BLOCK UVLO BIAS VOLTAGE + REFERENCE THERMAL LIMIT GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 OUT Regulated Output Voltage pin 2 N/C Not internally connected 3 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. 4 BIAS Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit. 5 GND Ground pin 6 IN Input Voltage Supply pin Pad Should be soldered to the ground plane for increased thermal performance. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 to 6 V IN Output Voltage V 0.3 to (V +0.3) 6 V OUT IN Chip Enable and Bias Input V V 0.3 to 6 V EN, BIAS Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22A114 ESD Machine Model tested per EIA/JESD22A115 Latchup Current Maximum Rating tested per JEDEC standard: JESD78. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, WDFN6 2 mm x 2 mm Thermal Resistance, JunctiontoAir (Note 3) R 65 C/W JA 3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted at the center of a high K (2s2p) 3in x 3in multilayer board with 1ounce internal planes and 2ounce copper on top and bottom. Top copper layer has a dedicated 125 sqmm copper area. www.onsemi.com 2