NCV8160 LDO Regulator - Ultra-Low Noise, High PSRR, RF and Analog Circuits 250 mA www.onsemi.com The NCV8160 is a linear regulator capable of supplying 250 mA output current. Designed to meet the requirements of RF and analog MARKING circuits, the NCV8160 device provides low noise, high PSRR, low DIAGRAM quiescent current, and very good load/line transients. The device is designed to work with a 1 F input and a 1 F output ceramic XDFN4 capacitor. It is available in XDFN4 0.65P, 1 mm x 1 mm. XX M CASE 711AJ 1 1 Features Operating Input Voltage Range: 1.9 V to 5.5 V XX = Specific Device Code Available in Fixed Voltage Option: 1.8 V to 5.14 V M = Date Code 2% Accuracy Over Temperature Ultra Low Quiescent Current Typ. 18 A PIN CONNECTIONS Standby Current: Typ. 0.1 A Very Low Dropout: 90 mV at 250 mA IN EN 4 3 Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz Ultra Low Noise: 10 V RMS Stable with a 1 F Small Case Size Ceramic Capacitors EPAD Available in XDFN4 1 mm x 1 mm x 0.4 mm NCV Prefix for Automotive and Other Applications Requiring 12 Unique Site and Control Change Requirements Grade 1 AECQ100 OUT GND Qualified and PPAP Capable (Top View) These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION Typical Applications See detailed ordering, marking and shipping information on page 13 of this data sheet. ADAS, Infotainment & Cluster, and Telematics General Purpose Automotive & Industrial Building & Factory Automation, Smart Meters V V OUT IN IN OUT NCV8160 C EN IN C OUT 1 F 1 F ON Ceramic Ceramic GND OFF Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: September, 2019 Rev. 2 NCV8160/DNCV8160 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. 2 GND Common ground connection 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN 4 IN Input voltage supply pin EPAD EPAD Expose pad can be tied to ground plane for better power dissipation www.onsemi.com 2