NCV8163 250 mA, Ultra-Low Noise and High PSRR LDO Regulator for RF and Analog Circuits www.onsemi.com The NCV8163 is a next generation of high PSRR, ultralow noise LDO capable of supplying 250 mA output current. Designed to meet the requirements of RF and sensitive analog circuits, the NCV8163 MARKING device provides ultralow noise, high PSRR and low quiescent DIAGRAMS current. The device also offer excellent load/line transients. The 5 NCV8163 is designed to work with a 1 F input and a 1 F output TSOP5 XXXAYW ceramic capacitor. It is available in XDFN4 0.65P, 1 mm x 1 mm and 5 CASE 483 TSOP5 packages. 1 1 Features XXX = Specific Device Code Operating Input Voltage Range: 2.2 V to 5.5 V A = Assembly Location Available in Fixed Voltage Option: 1.2 V to 5.3 V Y = Year W = Work Week 2% Accuracy Over Load/Temperature = PbFree Package Ultra Low Quiescent Current Typ. 12 A (Note: Microdot may be in either location) Standby Current: Typ. 0.1 A Very Low Dropout: 80 mV at 250 mA 3.3 V XDFN4 Ultra High PSRR: Typ. 92 dB at 20 mA, f = 1 kHz XX M CASE 711AJ 1 Ultra Low Noise: 6.5 V 1 RMS Stable with a 1 F Small Case Size Ceramic Capacitors XX = Specific Device Code Available in XDFN4 1 mm x 1 mm x 0.4 mm and TSOP5 Packages M = Date Code NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements Grade 1 AECQ100 PIN CONNECTIONS Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS IN15 OUT Compliant GND 2 Typical Applications ADAS, Infotainment & Cluster, and Telematics 34 NC EN General Purpose Automotive & Industrial (Top View) Building & Factory Automation, Smart Meters IN EN V 4 3 V OUT IN IN OUT NCV8163 EPAD C EN IN C OUT 1 F ON 1 F Ceramic Ceramic GND OFF 1 2 OUT GND (Top View) Figure 1. Typical Application Schematics ORDERING INFORMATION See detailed ordering, marking and shipping information on page 14 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2018 Rev. 3 NCV8163/DNCV8163 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin TSOP5 XDFN4 Name Description 1 4 IN Input voltage supply pin 5 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. 3 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN 2 2 GND Common ground connection 4 N/C Not connected. This pin can be tied to ground to improve thermal dissipation. EP EPAD Exposed Pad. Exposed pad can be tied to ground plane for better power dissipation. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 V to 6 V IN Output Voltage V 0.3 to V + 0.3, max. 6 V V OUT IN Chip Enable Input V 0.3 to 6 V V CE Output Short Circuit Duration t unlimited s SC Operating Ambient Temperature Range T 40 to +125 C A Maximum Junction Temperature T 150 C J Storage Temperature Range T 55 to +150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM ESD Capability, Charged Device Model (Note 2) ESD 1000 V CDM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22A114 ESD Machine Model tested per EIA/JESD22 A115 ESD Charged Device Model tested per EIA/JESD22C101, Field Induced Charge Model Latchup Current Maximum Rating tested per JEDEC standard: JESD78. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Max Unit Input Voltage V 2.2 5.5 V IN Junction Temperature T 40 +125 C J Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2