DATA SHEET www.onsemi.com Dual Operational Transconductance Amplifier 1 NE5517 SOIC16 D SUFFIX The NE5517 contains two current-controlled transconductance CASE 751B amplifiers, each with a differential input and push-pull output. The NE5517 offers significant design and performance advantages over MARKING DIAGRAM similar devices for all types of programmable gain applications. Circuit performance is enhanced through the use of linearizing diodes at the inputs which enable a 10 dB signal-to-noise improvement xx5517DG referenced to 0.5% THD. The NE5517 is suited for a wide variety of AWLYWW industrial and consumer applications. Constant impedance of the buffers on the chip allow general use of 1 the NE5517. These buffers are made of Darlington transistors and a biasing network that virtually eliminate the change of offset voltage xx = NE A = Assembly Location due to a burst in the bias current I , hence eliminating the audible ABC WL = Wafer Lot noise that could otherwise be heard in high quality audio applications. YY, Y = Year WW = Work Week Features G = PbFree Package Constant Impedance Buffers V of Buffer is Constant with Amplifier I Change BE BIAS PIN CONNECTIONS Excellent Matching Between Amplifiers 1 16 I I Linearizing Diodes ABCa ABCb D 2 15 D a b High Output Signal-to-Noise Ratio 3 14 +IN +IN a b This is a PbFree Device 4 13 IN IN a b Applications VO 5 12 VO a b Multiplexers V 6 11 V+ Timers 7 10 IN IN BUFFERa BUFFERb 8 9 Electronic Music Synthesizers VO VO BUFFERa BUFFERb Dolby HX Systems (Top View) Current-Controlled Amplifiers, Filters Current-Controlled Oscillators, Impedances ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: January, 2022 Rev. 5 NE5517/DNE5517 PIN DESCRIPTION Pin No. Symbol Description 1 I Amplifier Bias Input A ABCa 2 D Diode Bias A a 3 +IN Non-inverted Input A a 4 IN Inverted Input A a 5 VO Output A a 6 V Negative Supply 7 IN Buffer Input A BUFFERa 8 VO Buffer Output A BUFFERa 9 VO Buffer Output B BUFFERb 10 IN Buffer Input B BUFFERb 11 V+ Positive Supply 12 VO Output B b 13 IN Inverted Input B b 14 +IN Non-inverted Input B b 15 D Diode Bias B b 16 I Amplifier Bias Input B ABCb V+ 11 D4 D6 Q12 Q14 Q13 7,10 Q6 Q10 8,9 Q7 Q11 2,15 V D3 OUTPUT D2 Q4 5,12 Q5 +INPUT INPUT 3,14 4,13 Q15 Q16 1,16 Q3 AMP BIAS Q2 INPUT D7 Q9 R1 Q1 D8 Q8 D1 D5 V 6 Figure 1. Circuit Schematic www.onsemi.com 2