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Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdo nsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. MC14049UB Hex Buffers The MC14049UB hex inverter/buffer is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. This complementary MOS device finds primary use where low power dissipation and/or high noise immunity is desired. This device provides logiclevel conversion using only one www.onsemi.com supply voltage, V . The inputsignal high level (V ) can exceed the DD IH V supply voltage for logiclevel conversions. Two TTL/DTL DD MARKING Loads can be driven when the device is used as CMOStoTTL/DTL DIAGRAMS converters (V = 5.0 V, V 0.4 V, I 3.2 mA). Note that pins DD OL OL 16 13 and 16 are not connected internally on this device consequently SOIC16 connections to these terminals will not affect circuit operation. 14049UG D SUFFIX AWLYWW Features CASE 751B 1 High Source and Sink Currents HightoLow Level Converter 16 Supply Voltage Range = 3.0 V to 18 V 14 Meets JEDEC UB Specifications 049U TSSOP16 ALYW DT SUFFIX V can exceed V IN DD CASE 948F Improved ESD Protection on All Inputs 1 These Devices are PbFree and are RoHS Compliant 16 NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 SOEIAJ16 MC14049UB Qualified and PPAP Capable F SUFFIX ALYWG CASE 966 MAXIMUM RATINGS (Voltages Referenced to V ) SS 1 Symbol Parameter Value Unit V DC Supply Voltage Range 0.5 to +18.0 V DD A = Assembly Location WL, L = Wafer Lot V Input Voltage Range 0.5 to +18.0 V in YY, Y = Year (DC or Transient) WW, W = Work Week V Output Voltage Range 0.5 to V V out DD G or = PbFree Package (DC or Transient) +0.5 (Note: Microdot may be in either location) I Input Current 10 mA in (DC or Transient) per Pin I Output Current +45 mA out (DC or Transient) per Pin ORDERING INFORMATION See detailed ordering and shipping information in the package P Power Dissipation, per Package (Note 1) mW D dimensions section on page 3 of this data sheet. Plastic 825 SOIC 740 T Ambient Temperature Range 55 to +125 C A T Storage Temperature Range 65 to +150 C stg T Lead Temperature (8Second Soldering) 260 C L Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: All Packages: See Figure 4. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the V pin, only. Extra precautions SS must be taken to avoid applications of any voltage higher than the maximum rated voltages to this highimpedance circuit. For proper operation, the ranges V V 18 V and V V V are recommended. SS in SS out DD Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open. SS DD Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: June, 2017 Rev. 10 MC14049UB/D