NLAST4051 Analog Multiplexer/ Demultiplexer TTL Compatible, SinglePole, 8Position Plus Common Off www.onsemi.com The NLAST4051 is an improved version of the MC14051 and MC74HC4051 fabricated in submicron Silicon Gate CMOS technology MARKING for lower R resistance and improved linearity with low current. DS(on) DIAGRAM This device may be operated either with a single supply or dual supply up to 3 V to pass a 6 V signal without coupling capacitors. 16 PP When operating in single supply mode, it is only necessary to tie AST TSSOP16 V , pin 7 to ground. For dual supply operation, V is tied to a 4051 EE EE DT SUFFIX ALYW CASE 948F negative voltage, not to exceed maximum ratings. Translation is 1 provided in the device, the Address and Inhibit are standard TTL level 1 compatible. For CMOS compatibility see NLAS4051. Pin for pin A = Assembly Location compatible with all industry standard versions of 4051. L = Wafer Lot Features Y = Year W = Work Week Improved R Specifications DS(on) = PbFree Package Pin for Pin Replacement for MAX4051 and MAX4051A (Note: Microdot may be in either location) One Half the Resistance Operating at 5.0 V Single or Dual Supply Operation ORDERING INFORMATION Single 3.0 5.0 V Operation, or Dual 3 V Operation See detailed ordering and shipping information in the package With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, CC dimensions section on page 10 of this data sheet. No Translators Needed Address and Inhibit Logic are OverVoltage Tolerant and May Be Driven Up +6 V Regardless of V CC Address and Inhibit Pins Standard TTL Compatible Greatly Improved Noise Margin Over MAX4051 and MAX4051A True TTL Compatibility V = 0.8 V, V = 2.0 V IL IH Improved Linearity Over Standard HC4051 Devices Space Saving TSSOP Package NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant V NO NO NO NO ADD ADD ADD CC 2 4 0 6 C B A 16 15 14 13 12 11 10 9 1 2 345 67 8 NO NO COM NO NO Inhibit V GND 1 3 7 5 EE Figure 1. Pin Connection (Top View) Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: November, 2015 Rev. 5 NLAST4051/DNLAST4051 TRUTH TABLE NO 0 Inhibit Address ON SWITCHES* C B A NO 1 1 X X X All switches open NO dont care dont care dont care 2 0 0 0 0 COMNO 0 NO 3 0 0 0 1 COMNO COM 1 NO 4 0 0 1 0 COMNO 2 0 0 1 1 COMNO 3 NO 5 0 1 0 0 COMNO 4 NO 6 0 1 0 1 COMNO 5 0 1 1 0 COMNO 6 NO 7 0 1 1 1 COMNO ADD 7 C ADD LOGIC Inhibit B *NO and COM pins are identical and interchangeable. Either may be considered ADD A an input or output signals pass equally well in either direction. Figure 2. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit V Negative DC Supply Voltage (Referenced to GND) 7.0 to 0.5 V EE V Positive DC Supply Voltage (Note 1) (Referenced to GND) 0.5 to 7.0 V CC (Referenced to V ) 0.5 to 7.0 EE V Analog Input Voltage V 0.5 to V 0.5 V IS EE CC V Digital Input Voltage (Referenced to GND) 0.5 to 7.0 V IN I DC Current, Into or Out of Any Pin 50 mA T Storage Temperature Range 65 to 150 C STG T Lead Temperature, 1 mm from Case for 10 Seconds 260 C L T Junction Temperature under Bias 150 C J Thermal Resistance 164 C/W JA P Power Dissipation in Still Air 450 mW D MSL Moisture Sensitivity Level 1 F Flammability Rating Oxygen Index: 30% 35% UL 94 V0 0.125 in R V ESD Withstand Voltage Human Body Model (Note 2) 2000 V ESD Machine Model (Note 3) 200 Charged Device Model (Note 4) 1000 I Latchup Performance Above V and Below GND at 125C (Note 5) 300 mA LATCHUP CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The absolute value of V V 7.0. CC EE 2. Tested to EIA/JESD22A114A. 3. Tested to EIA/JESD22A115A. 4. Tested to JESD22C101A. 5. Tested to EIA/JESD78. www.onsemi.com 2