PEX8749, PCI Express Gen 3 Switch, 48 Lanes, 18 Ports Highlights The ExpressLane PEX8749 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective PEX8749 General Features o 48-lane, 18-port PCIe Gen 3 switch endpoints via scalable, high bandwidth, non-blocking interconnection to a Integrated 8.0 GT/s SerDes wide variety of applications including servers, storage, communications, and 2 o 27 x 27mm , 676-pin FCBGA package graphics platforms. The PEX8749 is well suited for fan-out, aggregation, o Typical Power: 7.3 Watts and peer-to-peer traffic patterns. PEX8749 Key Features Multi-Host Architecture o Standards Compliant The PEX8749 employs an enhanced version of PLXs field tested PEX8748 PCI Express Base Specification, r3.0 PCIe switch architecture, which allows users to configure the device in legacy (compatible w/ PCIe r1.0a/1.1 & 2.0) single-host mode or multi-host mode with up to six host ports capable of 1+1 PCI Power Management Spec, r1.2 Microsoft Vista Compliant (one active & one backup) or N+1 (N active & one backup) host failover. This Supports Access Control Services powerful architectural enhancement enables users to build PCIe based systems Dynamic link-width control to support high-availability, failover, redundant, or clustered systems. Dynamic SerDes speed control o High Performance High Performance & Low Packet Latency performancePAK The PEX8749 architecture supports packet cut-thru with a maximum Read Pacing (bandwidth throttling) latency of 126ns (x16 to x16). This, combined with large packet memory, Multicast Dynamic Buffer/FC Credit Pool flexible common buffer/FC credit pool and non-blocking internal switch Non-blocking switch fabric architecture, provides full line rate on all ports for performance-hungry Full line rate on all ports applications such as servers and switch fabrics. The low latency enables Packet Cut-Thru with 126ns max packet applications to achieve high throughput and performance. In addition to low latency (x16 to x16) latency, the device supports a packet payload size of up to 2048 bytes, 2KB Max Payload Size o Integrated DMA Engine enabling the user to achieve even higher throughput. Four DMA Channels Internal Descriptor Support Integrated DMA Engine DMA function independent from The PEX8749 boasts a versatile and powerful built-in DMA engine. The transparent switch function DMA engine removes the burden of having to move data between devices 64-bit Addressing away from the processor allowing the processor to perform computational Pre-fetch Descriptor Mode tasks instead. The four DMA channels can support high data rate transfers Stride Mode o Multi-Host & Fail-Over Support between I/O devices connected to any of the switchs ports. Additionally, the 2 Configurable Non-Transparent ports DMA engine in the PEX8749 can be used to complement the DMA engine in Failover with Non-Transparent port the processor by providing additional DMA channels for higher performance. Up to 6 upstream/Host ports with 1+1 or N+1 failover to other upstream ports Data Integrity o Quality of Service (QoS) The PEX8749 provides end-to-end CRC (ECRC) protection and Poison bit Two Virtual Channels support to enable designs that require end-to-end data integrity. PLX also Eight traffic classes per port Weighted round-robin source supports data path parity and memory (RAM) error correction circuitry port arbitration throughout the internal data paths as packets pass through the switch. o Reliability, Availability, Serviceability visionPAK Flexible Configuration x16 x8 Per Port Performance Monitoring The PEX8749s 18 ports can be SerDes Eye Capture configured to lane widths of x1, x2, x4, PCIe Packet Generator PPPPEEEEX 87X 87X 87X 8749494949 PPPPEEEEX 87X 87X 87X 8749494949 x8, or x16. Flexible buffer allocation, Error Injection and Loopback along with the device s flexible packet 3 Hot-Plug Ports with native HP Signals 2 All ports hot-plug capable thru I C flow control, maximizes throughput for 4 x8 10 x4 SSC Isolation on up to 12 ports applications where more traffic flows in ECRC and Poison bit support x8 x4 the downstream, rather than upstream, Data Path parity direction. Any port can be designated as Memory (RAM) Error Correction Advanced Error Reporting PPEEX 87X 874949 PPEEX 87X 874949 the upstream port, which can be changed PPEEX 87X 874949 PPEEX 87X 874949 Port Status bits and GPIO available dynamically. Figure 1 shows some of the JTAG AC/DC boundary scan PEX8749s common port configurations 6 x4 8 x2 17 x2 or x1 in legacy Single-Host mode. Figure 1. Single-Host Port Configurations PLX Technology, www.plxtech.com Page 1 of 5 22Aug11, version 1.0 PEX8749, PCI Express Gen 3 Switch, 48 Lanes, 18 Ports The PEX8749 can also be configured in Multi-Host mode Multi-Host & Failover Support where users can choose up to six ports as host/upstream In Multi-Host mode, PEX8749 can be configured with up ports and assign a desired number of downstream ports to to six upstream host ports, each with its own dedicated each host. In Multi-Host mode, a virtual switch is created downstream ports. The device can be configured for 1+1 for each host port and its associated downstream ports redundancy or N+1 redundancy. The PEX8749 allows the inside the device. The traffic between the ports of a virtual hosts to communicate their status to each other via special switch is completely isolated from the traffic in other door-bell registers. In failover mode, if a host fails, the virtual switches. Figure 2 illustrates some configurations host designated for failover will disable the upstream port of the PEX8749 in Multi-Host mode where each ellipse attached to the failing host and program the downstream represents a virtual switch inside the device. ports of that host to its own domain. Figure 4a shows a two host system in Multi-Host mode with two virtual switches x8 x8 x8 x4 x4 The PEX8749 inside the device and Figure 4b shows Host 1 disabled also provides after failure and Host 2 having taken over all of Host 1s several ways to end-points. configure its PPEEX 87X 874949 PPEEX 87X 874949 PPEEX 87X 874949 PPEEX 87X 874949 registers. The device can be configured 3 x8 2 x4 2 x8 2 x4 2 x4 through 4 x4s 3 x2s 2 x4s strapping pins, 2 I C interface, host software, or PPPPEEEEX 87X 87X 87X 8749494949 PPEEX 87X 874949 PPEEX 87X 874949 an optional serial EEPROM. Hot-Plug for High Availability This allows for Hot-plug capability allows users to replace hardware 8 x4s 9 x2s 4 x4s easy debug modules and perform maintenance without powering down Figure 2. Multi-Host Port Configurations during the the system. The PEX8749 hot plug capability feature development phase, performance monitoring during the makes it suitable for High Availability (HA) operation phase, and driver or software upgrade. applications. Three downstream ports include a Standard Hot Plug Controller. If the PEX8749 is used in an Dual-Host & Failover Support application where one or more of its downstream ports In Single-Host mode, the PEX8749 supports 2 Non- connect to PCI Express slots, each ports Hot-Plug Controller can be used to manage the hot-plug event of its Transparent (NT) Ports, PrPriimmararyy Ho Hostst SSeeconconddararyy Ho Hostst PrPriimmararyy Ho Hostst SSeeconconddararyy Ho Hostst which enables the associated slot. Every port on the PEX8749 is equipped CPUCPU CPUCPU CPUCPU CPUCPU implementation of with a hot-plug control/status register to support hot-plug 2 dual-host systems for capability through external logic via the I C interface. RootRoot RootRoot redundancy and host CompComplexlex CompComplexlex failover capability. The SerDes Power and Signal Management NT port allows systems The PEX8749 provides low power capability that is fully NT to isolate host memory compliant with the PCIe power management specification PPEEX 8X 8747499 Non-Transparent domains by presenting and supports software control of the SerDes outputs to Port the processor allow optimization of power and signal strength in a End End End End End End End End End End End End End End End End End End subsystem system. Furthermore, the SerDes block supports loop-back PoiPoiPointntnt PoiPoiPointntnt PoiPoiPointntnt PoiPoiPointntnt PoiPoiPointntnt PoiPoiPointntnt as an endpoint rather modes and advanced reporting of error conditions, Figure 3. Non-Transparent Port than another memory which enables efficient management of the entire system. system. Base address registers are used to translate addresses doorbell registers are used to send interrupts Interoperability between the address domains and scratchpad registers The PEX8749 is designed to be fully compliant with the (accessible by both CPUs) allow inter-processor PCI Express Base Specification r3.0, and is backwards communication (see Figure 3). compatible to PCI Express Base Specification r2.0, r1.1, PLX Technology, www.plxtech.com Page 2 of 5 22Aug11, version 1.0