CHY100 ChiPhy Family Charger Interface Physical Layer IC Product Highlights VOUT + D Fully supports Quick Charge 2.0 specification D- Class A: 5 V, 9 V, and 12 V output voltage GND Class B: 5 V, 9 V, 12 V, and 20 V output voltage USB battery charging specification revision 1.2 compatible + Automatic USB DCP shorting D to D- line Default 5 V mode operation BP Supports TOPSwitch and TinySwitch Very low power consumption V3 D+ Below 1 mW at 5 V output V2 D- CHY100 Fail safe operation Feedback U1 Adjacent pin-to-pin short-circuit fault Network V1 R Open circuit pin fault GND Typical Applications Battery chargers for smart phones, tablets, netbooks, digital PI-6988-071713 cameras, and bluetooth accessories Figure 1. Typical Application Schematic. USB power output ports Description CHY100 is a low-cost USB high-voltage dedicated charging port (HVDCP) interface IC for the Quick Charge 2.0 specification. It incorporates all necessary functions to add Quick Charge 2.0 capability to Power Integrations switcher ICs such as TOPSwitch or TinySwitch and other solutions employing traditional feedback SO-8 (D Package) schemes. Figure 2. Package Option. CHY100 supports the full output voltage range of either Class A or Class B. Optionally Class B can be inhibited for protecting the battery charger from accidental damage. CHY100 automatically detects whether a connected Powered Device (PD) is Quick Charge 2.0 capable before enabling output voltage adjustment. If a PD not compliant to Quick Charge 2.0 is detected the CHY100 disables output voltage adjustment to ensure safe operation with legacy 5 V only USB PDs. www.powerint.com March 2014 This Product is Covered by Patents and/or Pending Patent Applications.CHY100 REFERENCE BYPASS (R) (BP) BANDGAP + 3.9 V 6 V 2 V GND 0.325 V OUTPUT INHIBIT + D SET V3 CONTROL S Q LOGIC N5 D- (LOOKUP TABLE) R CLRQ N3 V2 0.325 V V1 N2 19.58 k 2 V N1 GROUND N4 (GND) PI-7009-071513 Figure 3. Functional Block Diagram. Pin Functional Description GROUND (GND) Pin Ground. D Package (SO-8) V1 Pin Open Drain input of output voltage adjustment switch. 1 8 Active for 9 V, 12 V, and 20 V output setting. GND BP 2 7 V1 R V2 Pin 3 6 Open Drain input of output voltage adjustment switch. V2 D+ Active for 12 V, and 20 V output setting. 4 5 V3 D- V3 Pin Open Drain input of output voltage adjustment switch. Active for 20 V output setting. PI-6987-071213 BYPASS (BP) Pin Figure 4. Pin Configuration. Connection point for an external bypass capacitor for the internally generated supply voltage. REFERENCE (R) Pin Connected to internal band-gap reference. Provides reference current through connected resistor. + DATA LINE D Pin + USB D data line input. - DATA LINE D Pin USB D- data line input. 2 Rev. C 03/14 www.powerint.com + + + +